Yong-Cheol Bae

According to our database1, Yong-Cheol Bae authored at least 7 papers between 2004 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution.
IEEE J. Solid State Circuits, 2017


2016
Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM).
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation.
IEEE J. Solid State Circuits, 2015

A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface.
Proceedings of the Symposium on VLSI Circuits, 2015

2012
A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2004
A mixed PLL/DLL architecture for low jitter clock generation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004


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