Andre Guntoro
Orcid: 0000-0003-4144-0283
According to our database1,
Andre Guntoro
authored at least 52 papers
between 2002 and 2024.
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Bibliography
2024
CoRR, 2024
2023
Proceedings of the Computer Safety, Reliability, and Security, 2023
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023
2022
FELIX: A Ferroelectric FET Based Low Power Mixed-Signal In-Memory Architecture for DNN Acceleration.
ACM Trans. Embed. Comput. Syst., November, 2022
Increasing Throughput of In-Memory DNN Accelerators by Flexible Layerwise DNN Approximation.
IEEE Micro, 2022
A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Efficient Hardware Approximation for Bit-Decomposition Based Deep Neural Network Accelerators.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
Fault-tolerant Radar Signal Processing using Selective Observation Windows and Peak Detection.
Proceedings of the 30th European Signal Processing Conference, 2022
2021
Exploiting Resiliency for Kernel-Wise CNN Approximation Enabled by Adaptive Hardware Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Knowledge Distillation and Gradient Estimation for Active Error Compensation in Approximate Neural Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Efficient Accuracy Recovery in Approximate Neural Networks by Systematic Error Modelling.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Adaptable Approximation Based on Bit Decomposition for Deep Neural Network Accelerators.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
Neural Comput. Appl., 2020
Improving approximate neural networks for perception tasks through specialized optimization.
Future Gener. Comput. Syst., 2020
A Ferroelectric FET Based In-memory Architecture for Multi-Precision Neural Networks.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 28th European Signal Processing Conference, 2020
ProxSim: GPU-based Simulation Framework for Cross-Layer Approximate DNN Optimization.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020
2019
An End-to-End HW/SW Co-Design Methodology to Design Efficient Deep Neural Network Systems using Virtual Models.
Proceedings of the INTESA 2019 Proceedings, 2019
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019
Self-Supervised Quantization of Pre-Trained Neural Networks for Multiplierless Acceleration.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Guaranteed Compression Rate for Activations in CNNs using a Frequency Pruning Approach.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Efficient On-Line Error Detection and Mitigation for Deep Neural Network Accelerators.
Proceedings of the Computer Safety, Reliability, and Security, 2018
Efficient hardware acceleration of CNNs using logarithmic data representation with arbitrary log-base.
Proceedings of the International Conference on Computer-Aided Design, 2018
Accurate neuron resilience prediction for a flexible reliability management in neural network accelerators.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Efficient hardware acceleration for approximate inference of bitwise deep neural networks.
Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017
2016
2009
Algorithm, Application Mapping, Design and Realization of the Time-Frequency Representation with Flexible Kernels based on their Lifting Scheme
PhD thesis, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
A Lifting-Based Discrete Wavelet Transform and Discrete Wavelet Packet Processor with Support for Higher Order Wavelet Filters.
Proceedings of the VLSI-SoC: Design Methodologies for SoC and SiP, 2008
Proceedings of the 4th IEEE International Conference on Signal Image Technology and Internet Based Systems, 2008
Configurable VLSI Architecture of a General Purpose Lifting-based Wavelet Processor.
Proceedings of the SIGMAP 2008, 2008
High-Speed Configurable VLSI Architecture of a General Purpose Lifting-Based Discrete Wavelet Processor.
Proceedings of the e-Business and Telecommunications - International Conference, 2008
Proceedings of the FPL 2008, 2008
A lifting-based DWT and IDWT processor with multi-context configuration and normalization factor.
Proceedings of the FPL 2008, 2008
Novel approach on lifting-based DWT and IDWT processor with multi-context configuration to support different wavelet filters.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008
Impact of circuit nonidealities on the implementation of switched-capacitor resonators.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
High-performance floating-point VLSI architecture of lifting-based forward and inverse wavelet transforms.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive Coupling.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007
2006
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006
2005
Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005
2002
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002