Leibin Ni

According to our database, Leibin Ni authored at least 23 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier.

Laimin Du, Leibin Ni, Xiong Liu, Guanqi Peng, Kai Li, Wei Mao, Hao Yu

IEEE Open J. Circuits Syst., 2024

AFPR-CIM: An Analog-Domain Floating-Point RRAM-based Compute-In-Memory Architecture with Dynamic Range Adaptive FP-ADC.

Haobo Liu, Zhengyang Qian, Wei Wu, Hongwei Ren, Zhiwei Liu, Leibin Ni

CoRR, 2024

2023

High-accuracy Low-power Reconfigurable Architectures for Decomposition-based Approximate Lookup Table.

Xingyue Qian, Chang Meng, Xiaolong Shen, Junfeng Zhao, Leibin Ni, Weikang Qian

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

VECBEE: A Versatile Efficiency-Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis.

Sanbao Su, Chang Meng, Fan Yang, Xiaolong Shen, Leibin Ni, Wei Wu, Zhihang Wu, Junfeng Zhao, Weikang Qian

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Investigation of Pass Transistor Logic in a 12nm FinFET CMOS Technology.

André Lucas Chinazzo, Jan Lappas, Christian Weis, Qinhui Huang, Zhihang Wu, Leibin Ni, Norbert Wehn

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

Machine learning based soft error rate estimation of pass transistor logic in high-speed communication.

Zhe Zhang, Jan Lappas, André Lucas Chinazzo, Christian Weis, Zhihang Wu, Leibin Ni, Norbert Wehn, Mehdi B. Tahoori

Proceedings of the IEEE European Test Symposium, 2022

Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology Node.

Jan Lappas, André Lucas Chinazzo, Christian Weis, Chenyang Xia, Zhihang Wu, Leibin Ni, Norbert Wehn

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

SEALS: sensitivity-driven efficient approximate logic synthesis.

Chang Meng, Xuan Wang, Jiajun Sun, Sijun Tao, Wei Wu, Zhihang Wu, Leibin Ni, Xiaolong Shen, Junfeng Zhao, Weikang Qian

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

A Low-Power Approximate Multiplier with Sign-Focus Compressor and Error Compensation.

Laimin Du, Leibin Ni, Xiong Liu, Wei Mao, Hao Yu

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2019

A Low-Power High-Throughput In-Memory CMOS-ReRAM Accelerator for Large-Scale Deep Residual Neural Networks.

Yuan Cheng, Ngai Wong, Xiong Liu, Leibin Ni, Hai-Bao Chen, Hao Yu

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2017

Distributed In-Memory Computing on Binary RRAM Crossbar.

Leibin Ni, Hantao Huang, Zichuan Liu, Rajiv V. Joshi, Hao Yu

ACM J. Emerg. Technol. Comput. Syst., 2017

LTNN: An energy-efficient machine learning accelerator on 3D CMOS-RRAM for layer-wise tensorized neural network.

Hantao Huang, Leibin Ni, Hao Yu

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

An energy-efficient and high-throughput bitwise CNN on sneak-path-free digital ReRAM crossbar.

Leibin Ni, Zichuan Liu, Wenhao Song, J. Joshua Yang, Hao Yu, Kanwen Wang, Yuangang Wang

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

2016

Non-Volatile In-Memory Computing by Spintronics

Hao Yu, Leibin Ni, Yuhao Wang

Synthesis Lectures on Emerging Engineering Technologies, Morgan & Claypool Publishers, ISBN: 978-3-031-02032-2, 2016

DW-AES: A Domain-Wall Nanowire-Based AES for High Throughput and Energy-Efficient Data Encryption in Non-Volatile Memory.

Yuhao Wang, Leibin Ni, Chip-Hong Chang, Hao Yu

IEEE Trans. Inf. Forensics Secur., 2016

A Zonotoped Macromodeling for Eye-Diagram Verification of High-Speed I/O Links With Jitter and Parameter Variations.

Leibin Ni, Sai Manoj P. D., Yang Song, Chenjie Gu, Hao Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Racetrack memory-based encoder/decoder for low-power interconnect architectures.

Suman Deb, Leibin Ni, Hao Yu, Anupam Chattopadhyay

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

A memristor network with coupled oscillator and crossbar towards L2-norm based machine learning.

Leibin Ni, Hantao Huang, Hao Yu

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

On-line machine learning accelerator on digital RRAM-crossbar.

Leibin Ni, Hantao Huang, Hao Yu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar.

Leibin Ni, Yuhao Wang, Hao Yu, Wei Yang, Chuliang Weng, Junfeng Zhao

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

A 3D multi-layer CMOS-RRAM accelerator for neural network.

Hantao Huang, Leibin Ni, Yuhao Wang, Hao Yu, Zongwei Wang, Yimao Cai, Ru Huang

Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015

Optimizing Boolean embedding matrix for compressive sensing in RRAM crossbar.

Yuhao Wang, Xin Li, Hao Yu, Leibin Ni, Wei Yang, Chuliang Weng, Junfeng Zhao

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

An energy-efficient non-volatile in-memory accelerator for sparse-representation based face recognition.

Yuhao Wang, Hantao Huang, Leibin Ni, Hao Yu, Mei Yan, Chuliang Weng, Wei Yang, Junfeng Zhao

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015