Jayeeta Chaudhuri
Orcid: 0000-0002-6738-805X
According to our database1,
Jayeeta Chaudhuri
authored at least 15 papers
between 2022 and 2025.
Collaborative distances:
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Bibliography
2025
LATENT: LLM-Augmented Trojan Insertion and Evaluation Framework for Analog Netlist Topologies.
CoRR, May, 2025
SPICED+: Syntactical Bug Pattern Identification and Correction of Trojans in A/MS Circuits Using LLM-Enhanced Detection.
IEEE Trans. Very Large Scale Integr. Syst., April, 2025
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2025
Proceedings of the 43rd IEEE VLSI Test Symposium, 2025
FLARE: Fault Attack Leveraging Address Reconfiguration Exploits in Multi-Tenant FPGAs.
Proceedings of the IEEE European Test Symposium, 2025
2024
DAWN: Efficient Trojan Detection in Analog Circuits Using Circuit Watermarking and Neural Twins.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024
SPICED: Syntactical Bug and Trojan Pattern Identification in A/MS Circuits using LLM-Enhanced Detection.
CoRR, 2024
Proceedings of the IEEE European Test Symposium, 2024
Hacking the Fabric: Targeting Partial Reconfiguration for Fault Injection in FPGA Fabrics.
Proceedings of the 33rd IEEE Asian Test Symposium, 2024
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
Proceedings of the 21st IEEE International Conference on Machine Learning and Applications, 2022
Proceedings of the IEEE European Test Symposium, 2022