Jerry R. Burch

According to our database1, Jerry R. Burch authored at least 32 papers between 1985 and 2007.

Collaborative distances:
  • Dijkstra number2 of two.
  • Erdős number3 of four.

Timeline

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Bibliography

2007
Refinement preserving approximations for the design and verification of heterogeneous systems.
Formal Methods Syst. Des., 2007

Memory Modeling in ESL-RTL Equivalence Checking.
Proceedings of the 44th Design Automation Conference, 2007

2006
Linear cofactor relationships in Boolean functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Using simulation and satisfiability to compute flexibilities in Boolean networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2005
Detecting support-reducing bound sets using two-cofactor symmetries.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Conservative approximations for heterogeneous design.
Proceedings of the EMSOFT 2004, 2004

2001
Constraints specification at higher levels of abstraction.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

Using Multiple Levels of Abstractions in Embedded Software Design.
Proceedings of the Embedded Software, First International Workshop, 2001

Overcoming Heterophobia: Modeling Concurrency in Heterogeneous Systems.
Proceedings of the 2nd International Conference on Application of Concurrency to System Design (ACSD 2001), 2001

2000
Sibling-substitution-based BDD minimization using don't cares.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1998
Checking Combinational Equivalence of Speed-Independent Circuits.
Formal Methods Syst. Des., 1998

Tight integration of combinational verification methods.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Robust latch mapping for combinational equivalence checking.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997
Safe BDD Minimization Using Don't Cares.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Mechanically Checking a Lemma Used in an Automatic Verification Tool.
Proceedings of the Formal Methods in Computer-Aided Design, First International Conference, 1996

Techniques for Verifying Superscalar Microprocessors.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Efficient validity checking for processor verification.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994
Symbolic model checking for sequential circuit verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Automatic verification of Pipelined Microprocessor Control.
Proceedings of the Computer Aided Verification, 6th International Conference, 1994

Sufficient conditions for correct gate-level speed-independent circuits.
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994

1993
Modeling hierarchical combinational circuits.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Efficient verification of determinate speed-independent circuits.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992
Symbolic Model Checking: 10^20 States and Beyond
Inf. Comput., June, 1992

Delay Models for Verifying Speed-Dependent Asynchronous Circuits.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Efficient Boolean function matching.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1991
Symbolic Model Checking with Partitioned Transistion Relations.
Proceedings of the VLSI 91, 1991

Representing Circuits More Efficiently in Symbolic Model Checking.
Proceedings of the 28th Design Automation Conference, 1991

Using BDDs to Verify Multipliers.
Proceedings of the 28th Design Automation Conference, 1991

1990
Sequential Circuit Verification Using Symbolic Model Checking.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Verifying Liveness Properties by Verifying Safety Properties.
Proceedings of the Computer Aided Verification, 2nd International Workshop, 1990

1989
Combining CTL, Trace Theory and Timing Models.
Proceedings of the Automatic Verification Methods for Finite State Systems, 1989

1985
Fair Mutual Exclusion with Unfair P and V Operations.
Inf. Process. Lett., 1985


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