Vigyan Singhal

Prashant Aggarwal

Proceedings of the Computer Aided Verification - 23rd International Conference, 2011

2008

Formal Verification of a Public-Domain DDR2 Controller Design.

[BibT_eX]

[DOI]

Abhishek Datta

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2003

Sequential optimization in the absence of global reset.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2003

BDD Based Procedures for a Theory of Equality with Uninterpreted Functions.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2003

An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2003

2002

Formula-Dependent Equivalence for Compositional CTL Model Checking.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2002

2001

Optimizing designs containing black boxes.

[BibT_eX]

[DOI]

Tai-Hung Liu

ACM Trans. Design Autom. Electr. Syst., 2001

Theory of safe replacements for sequential circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

SIVA: A System for Coverage-Directed State Space Search.

[BibT_eX]

[DOI]

J. Electron. Test., 2001

2000

Model-checking continous-time Markov chains.

[BibT_eX]

[DOI]

ACM Trans. Comput. Log., 2000

Automatic Lighthouse Generation for Directed State Space Search.

[BibT_eX]

[DOI]

Praveen Yalagandula

Proceedings of the 2000 Design, 2000

BDS: a BDD-based logic optimization system.

[BibT_eX]

[DOI]

Congguang Yang

Maciej J. Ciesielski

Proceedings of the 37th Conference on Design Automation, 2000

An Abstraction Algorithm for the Verification of Generalized C-Slow Designs.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 12th International Conference, 2000

1999

Model Checking: A Hardware Design Perspective.

[BibT_eX]

[DOI]

Carl Pixley

Int. J. Softw. Tools Technol. Transf., 1999

Equivalences for Fair Kripke Structures.

[BibT_eX]

[DOI]

Chic. J. Theor. Comput. Sci., 1999

BDD Decomposition for Efficient Logic Synthesis.

[BibT_eX]

[DOI]

Congguang Yang

Maciej J. Ciesielski

Proceedings of the IEEE International Conference On Computer Design, 1999

Using Combinational Verification for Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 11th International Conference, 1999

1998

On the optimization power of retiming and resynthesis transformations.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Tight integration of combinational verification methods.

[BibT_eX]

[DOI]

Jerry R. Burch

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Robust latch mapping for combinational equivalence checking.

[BibT_eX]

[DOI]

Jerry R. Burch

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997

Analysis of Locking Behavior in Three Real Database Systems.

[BibT_eX]

[DOI]

Alan Jay Smith

VLDB J., 1997

Sequential optimisation without state space exploration.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Optimizing Designs Containing Black Boxes.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

1996

Latch Redundancy Removal Without Global Reset.

[BibT_eX]

[DOI]

Shaz Qadeer

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

The case for retiming with explicit reset circuitry.

[BibT_eX]

[DOI]

Sharad Malik

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Verifying Continuous Time Markov Chains.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 8th International Conference, 1996

1995

Power-Up Delay for Retiming Digital Circuits.

[BibT_eX]

[DOI]

Carl Pixley

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Incremental methods for FSM traversal.

[BibT_eX]

[DOI]

Gitanjali Swamy

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Exploiting power-up delay for sequential optimization.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'95, 1995

The Validity of Retiming Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the 32st Conference on Design Automation, 1995

It Usually Works: The Temporal Logic of Stochastic Systems.

[BibT_eX]

[DOI]

Felice Balarin

Proceedings of the Computer Aided Verification, 1995

1994

Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Multi-level synthesis for safe replaceability.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

HSIS: A BDD-Based Environment for Formal Verification.

[BibT_eX]

[DOI]

Proceedings of the 31st Conference on Design Automation, 1994

The Verifiacation Problem for Safe Replaceability.

[BibT_eX]

[DOI]

Carl Pixley

Proceedings of the Computer Aided Verification, 6th International Conference, 1994

Formula-Dependent Equivalence for Compositional CTL Model Checking.

[BibT_eX]

[DOI]

Thomas R. Shiple

Proceedings of the Computer Aided Verification, 6th International Conference, 1994

1993

Heuristic Minimization of Synchronous Relations.

[BibT_eX]

[DOI]

Yosinori Watanabe