Ji-Hak Yu
According to our database1,
Ji-Hak Yu
authored at least 5 papers
between 2015 and 2025.
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Bibliography
2025
30.3 A 24Gb 42.5Gb/s GDDR7 DRAM with Low-Power WCK Distribution, an RC-Optimized Dual-Emphasis TX, and Voltage/Time-Margin-Enhanced Power Reduction.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
2019
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking.
IEEE J. Solid State Circuits, 2019
2018
A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2016
A 2ps minimum-resolution, wide-input-range time-to-digital converter for the time-of-flight measurement using cyclic technique and time amplifier.
Proceedings of the IEEE International Conference on Consumer Electronics, 2016
2015
Proceedings of the International Symposium on Consumer Electronics, 2015