According to our database1, Youn-Sik Park authored at least 12 papers between 1993 and 2020.
Legend:Book In proceedings Article PhD thesis Other
IEEE J. Solid State Circuits, 2020
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking.
IEEE J. Solid State Circuits, 2019
A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM.
IEEE J. Solid State Circuits, 2018
A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM.
Proceedings of the 52nd Annual Design Automation Conference, 2015
PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Experimental evaluation of time-varying impulse shaping with a two-link flexible manipulator.
Fourier-based optimal design of a flexible manipulator path to reduce residual vibration of the endpoint.