Sam-Young Bang
According to our database1,
Sam-Young Bang
authored at least 8 papers
between 2007 and 2019.
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Bibliography
2019
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking.
IEEE J. Solid State Circuits, 2019
2018
A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2011
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction.
IEEE J. Solid State Circuits, 2011
A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2008
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion.
IEEE J. Solid State Circuits, 2008
A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007