Dong-Seok Kang
According to our database1,
Dong-Seok Kang
authored at least 8 papers
between 2008 and 2020.
Collaborative distances:
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Bibliography
2020
A 4-GHz Sub-Harmonically Injection-Locked Phase-Locked Loop With Self-Calibrated Injection Timing and Pulsewidth.
IEEE J. Solid State Circuits, 2020
Proceedings of the 22nd International Conference on Advanced Communication Technology, 2020
2019
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking.
IEEE J. Solid State Circuits, 2019
A 4-GHz Sub-harmonically Injection-Locked Phase-Locked Loop with Self-Calibrated Injection Timing and Pulsewidth.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 4.0-10.0-Gb/s Referenceless CDR with Wide-Range, Jitter-Tolerant, and Harmonic-Lock-Free Frequency Acquisition Technique.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
2011
A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2008
Case Study on the Effects of Administrative Informatization on the Organizational Structure for the Central Government in Korea.
Proceedings of the Electronic Government, 7th International Conference, 2008