Jianwen Zhu

Affiliations:
  • University of Toronto, Canada


According to our database1, Jianwen Zhu authored at least 62 papers between 1998 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2023
Multi-constrained intelligent gliding guidance via optimal control and DQN.
Sci. China Inf. Sci., March, 2023

2020
Rotary Register File: A Micro-Architectural Primitive on FPGA.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2017
A fast Bayesian algorithmic enhancement for real time bit error ratio test (BERT).
Proceedings of the 2017 IEEE Global Conference on Signal and Information Processing, 2017

A Case for Common-Case: On FPGA Acceleration of Erasure Coding.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

2016
Write Skew and Zipf Distribution: Evidence and Implications.
ACM Trans. Storage, 2016

Write Amplification with Write Skew.
Proceedings of the 24th IEEE International Symposium on Modeling, 2016

2015
A Sufficient Condition for Deadlock-Free Adaptive Routing in Mesh Networks.
IEEE Comput. Archit. Lett., 2015

Algebraic modeling of write amplification in hotness-aware SSD.
Proceedings of the 8th ACM International Systems and Storage Conference, 2015

2014
Analytical modeling of garbage collection algorithms in hotness-aware flash-based solid state drives.
Proceedings of the IEEE 30th Symposium on Mass Storage Systems and Technologies, 2014

2012
Saturating the transceiver bandwidth: switch fabric design on FPGAs.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

2011
Toward Automated ECOs in FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Timing-Driven Routing of High Fanout Nets.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Regular fabric for regular FPGA (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

A bursty multi-port memory controller with quality-of-service guarantees.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Register pressure aware scheduling for high level synthesis.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

On virtual prototyping of embedded system-on-chips.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Interprocedural induction variable analysis based on interprocedural SSA form IR.
Proceedings of the 9th ACM SIGPLAN-SIGSOFT Workshop on Program Analysis for Software Tools and Engineering, 2010

Using variable clocking to reduce leakage in synchronous circuits.
Proceedings of the 28th International Conference on Computer Design, 2010

Credit Borrow and Repay: Sharing DRAM with minimum latency and bandwidth guarantees.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Parallelizing Simulated Annealing-Based Placement Using GPGPU.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

A 1 cycle-per-byte XML parsing accelerator.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Towards scalable placement for FPGAs.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2009
Increasing the Scope and Resolution of Interprocedural Static Single Assignment.
Proceedings of the Static Analysis, 16th International Symposium, 2009

VariPipe: Low-overhead variable-clock synchronous pipelines.
Proceedings of the 27th International Conference on Computer Design, 2009

Towards automated ECOs in FPGAs.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2008
Scalable Synthesis and Clustering Techniques Using Decision Diagrams.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Delay driven AIG restructuring using slack budget management.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007
BddCut: Towards Scalable Symbolic Cut Enumeration.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Dynamic-range estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2005
Calligrapher: a new layout-migration engine for hard intellectual property libraries.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Context sensitive symbolic pointer analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Two-Dimensional Layout Migration by Soft Constraint Satisfaction.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Towards scalable flow and context sensitive pointer analysis.
Proceedings of the 42nd Design Automation Conference, 2005

A non-parametric approach for dynamic range estimation of nonlinear systems.
Proceedings of the 42nd Design Automation Conference, 2005

BDD-based two variable sharing extraction.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Scalable interprocedural register allocation for high level synthesis.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Symbolic pointer analysis revisited.
Proceedings of the ACM SIGPLAN 2004 Conference on Programming Language Design and Implementation 2004, 2004

Stacked FSMD: A Power Efficient Micro-Architecture for High Level Synthesis.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Calligrapher: A New Layout Migration Engine Based on Geometric Closeness.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Dynamic range estimation for nonlinear systems.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

DynamoSim: a trace-based dynamically compiled instruction set simulator.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

A queuing-theoretic performance model for context-flow system-on-chip platforms.
Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia, 2004

An analytical approach for dynamic range estimation.
Proceedings of the 41th Design Automation Conference, 2004

Piecewise quadratic waveform matching with successive chord iteration.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Automatic process migration of datapath hard IP libraries.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Performance Efficiency of Context-Flow System-on-Chip Platform.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Specification of Non-Functional Intellectual Property Components.
Proceedings of the 2003 Design, 2003

Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching.
Proceedings of the 2003 Design, 2003

A retargetable micro-architecture simulator.
Proceedings of the 40th Design Automation Conference, 2003

2002
An ultra-fast instruction set simulator.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Symbolic pointer analysis.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Hardware Implementation of a Memory Allocator.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

Retargetable binary utilities.
Proceedings of the 39th Design Automation Conference, 2002

2001
Color Permutation: An Iterative Algorithm for Memory Packing.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Static memory allocation by pointer analysis and coloring.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

MetaRTL: raising the abstraction level of RTL design.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Compiling SpecC for simulation.
Proceedings of ASP-DAC 2001, 2001

1999
OpenJ: An Extensible System Level Design Language.
Proceedings of the 1999 Design, 1999

Soft Scheduling in High Level Synthesis.
Proceedings of the 36th Conference on Design Automation, 1999

A unified formal model of ISA and FSMD.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998
Specification and Design of Embedded Systems.
Informationstechnik Tech. Inform., 1998

IP-Centric Methodology and Specification Language.
Proceedings of the Distributed and Parallel Embedded Systems, 1998


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