Stephen Dean Brown

According to our database, Stephen Dean Brown authored at least 82 papers between 1992 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2018

Use of CPU Performance Counters for Accelerator Selection in HLS-Generated CPU-Accelerator Systems.

Bain Syrowik, Blair Fort, Stephen Dean Brown

Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

2017

From Pthreads to Multicore Hardware Systems in LegUp High-Level Synthesis for FPGAs.

Jongsok Choi, Stephen Dean Brown, Jason Helge Anderson

IEEE Trans. Very Large Scale Integr. Syst., 2017

FISH: Linux system calls for FPGA accelerators.

Kevin Nam, Blair Fort, Stephen Dean Brown

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016

A Survey and Evaluation of FPGA High-Level Synthesis Tools.

Razvan Nane, Vlad Mihai Sima, Christian Pilato, Jongsok Choi, Blair Fort, Andrew Canis, Yu Ting Chen, Hsuan Hsiao, Stephen Dean Brown, Fabrizio Ferrandi, Jason Helge Anderson, Koen Bertels

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A unified software approach to specify pipeline and spatial parallelism in FPGA hardware.

Jongsok Choi, Ruolong Lian, Stephen Dean Brown, Jason Helge Anderson

Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

LegUp High-Level Synthesis.

Andrew Canis, Jongsok Choi, Blair Fort, Bain Syrowik, Ruolong Lian, Yu Ting Chen, Hsuan Hsiao, Jeffrey B. Goeders, Stephen Dean Brown, Jason Helge Anderson

Proceedings of the FPGAs for Software Programmers, 2016

2015

The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware.

Qijing Huang, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson

ACM Trans. Reconfigurable Technol. Syst., 2015

Resource and memory management techniques for the high-level synthesis of software threads into parallel FPGA hardware.

Jongsok Choi, Stephen Dean Brown, Jason Helge Anderson

Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

2014

Modulo SDC scheduling with recurrence minimization in high-level synthesis.

Andrew Canis, Stephen Dean Brown, Jason Helge Anderson

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Source-level debugging for FPGA high-level synthesis.

Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis.

Blair Fort, Andrew Canis, Jongsok Choi, Nazanin Calagar, Ruolong Lian, Stefan Hadjis, Yu Ting Chen, Mathew Hall, Bain Syrowik, Tomasz S. Czajkowski, Stephen Dean Brown, Jason Helge Anderson

Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

2013

Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAs.

Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown

ACM Trans. Reconfigurable Technol. Syst., 2013

LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems.

Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Tomasz S. Czajkowski, Stephen Dean Brown, Jason Helge Anderson

ACM Trans. Embed. Comput. Syst., 2013

From software threads to parallel hardware in high-level synthesis for FPGAs.

Jongsok Choi, Stephen Dean Brown, Jason Helge Anderson

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

From C to Blokus Duo with LegUp high-level synthesis.

Jiu Cheng Cai, Ruolong Lian, Mengyao Wang, Andrew Canis, Jongsok Choi, Blair Fort, Eric Hart, Emily Miao, Yanyan Zhang, Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

High-level synthesis with LegUp: a crash course for users and researchers.

Jason Helge Anderson, Stephen Dean Brown, Andrew Canis, Jongsok Choi

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs.

Qijing Huang, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Stephen Dean Brown, Jason Helge Anderson

Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Multi-pumping for resource reduction in FPGA high-level synthesis.

Andrew Canis, Jason Helge Anderson, Stephen Dean Brown

Proceedings of the Design, Automation and Test in Europe, 2013

From software to accelerators with LegUp high-level synthesis.

Andrew Canis, Jongsok Choi, Blair Fort, Ruolong Lian, Qijing Huang, Nazanin Calagar, Marcel Gort, Jia Jun Qin, Mark Aldham, Tomasz S. Czajkowski, Stephen Dean Brown, Jason Helge Anderson

Proceedings of the International Conference on Compilers, 2013

2012

Impact of FPGA architecture on resource sharing in high-level synthesis.

Stefan Hadjis, Andrew Canis, Jason Helge Anderson, Jongsok Choi, Kevin Nam, Stephen Dean Brown, Tomasz S. Czajkowski

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems.

Jongsok Choi, Kevin Nam, Andrew Canis, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski

Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2011

Toward Automated ECOs in FPGAs.

Andrew C. Ling, Stephen Dean Brown, Sean Safarpour, Jianwen Zhu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

LegUp: high-level synthesis for FPGA-based processor/accelerator systems.

Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Low-cost hardware profiling of run-time and energy in FPGA embedded processors.

Mark Aldham, Jason Helge Anderson, Stephen Dean Brown, Andrew Canis

Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

2010

Decomposition-Based Vectorless Toggle Rate Computation for FPGA Circuits.

Tomasz S. Czajkowski, Stephen Dean Brown

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2009

Enhancements to FPGA design methodology using streaming.

Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Towards automated ECOs in FPGAs.

Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2008

Scalable Synthesis and Clustering Techniques Using Decision Diagrams.

Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs.

Tomasz S. Czajkowski, Stephen Dean Brown

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Delay driven AIG restructuring using slack budget management.

Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Fast toggle rate computation for FPGA circuits.

Tomasz S. Czajkowski, Stephen Dean Brown

Proceedings of the FPL 2008, 2008

Stream Programming for FPGAs.

Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown

Proceedings of the Languages for Embedded Systems and their Applications, 2008

Towards Compilation of Streaming Programs into FPGA Hardware.

Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown

Proceedings of the Forum on specification and Design Languages, 2008

2007

Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow.

Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown

IEEE Trans. Very Large Scale Integr. Syst., 2007

FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability.

Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

An area-efficient timing closure technique for FPGAs using Shannon's expansion.

Deshanand P. Singh, Stephen Dean Brown

Integr., 2007

Incremental placement for structured ASICs using the transportation problem.

Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown

Proceedings of the IFIP VLSI-SoC 2007, 2007

On Digital Search Trees - A Simple Method for Constructing Balanced Binary Trees.

Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown

Proceedings of the ICSOFT 2007, 2007

Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits.

Tomasz S. Czajkowski, Stephen Dean Brown

Proceedings of the 44th Design Automation Conference, 2007

BddCut: Towards Scalable Symbolic Cut Enumeration.

Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping.

Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow.

Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown

Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs.

Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Adaptive FPGAs: High-Level Architecture and a Synthesis Method.

Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Modular Partitioning for Incremental Compilation.

Mehrdad Eslami Dehkordi, Stephen Dean Brown, Terry P. Borer

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A Multithreaded Soft Processor for SoPC Area Reduction.

Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

2005

FPGA Logic Synthesis Using Quantified Boolean Satisfiability.

Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown

Proceedings of the Theory and Applications of Satisfiability Testing, 2005

Experiences with Soft-Core Processor Design.

Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen Dean Brown

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Post-Placement BDD-Based Decomposition for FPGAs.

Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

FPGA PLB Evaluation using Quantified Boolean Satisfiability.

Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Incremental retiming for FPGA physical synthesis.

Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown

Proceedings of the 42nd Design Automation Conference, 2005

FPGA technology mapping: a study of optimality.

Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown

Proceedings of the 42nd Design Automation Conference, 2005

Two-stage physical synthesis for FPGAs.

Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004

The Quartus University Interface Program: enabling advanced FPGA research.

Shawn Malhotra, Terry P. Borer, Deshanand P. Singh, Stephen Dean Brown

Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Retiming aware clustering for sequential circuits.

Mehrdad Eslami Dehkordi, Stephen Dean Brown

Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

2003

Use of HDLs in teaching of computer hardware courses.

Zvonko G. Vranesic, Stephen Dean Brown

Proceedings of the 2003 workshop on Computer architecture education, 2003

Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices.

Deshanand P. Singh, Terry P. Borer, Stephen Dean Brown

Proceedings of the International Conference on VLSI, 2003

Performance-driven recursive multi-level clustering.

Mehrdad Eslami Dehkordi, Stephen Dean Brown

Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Recursive circuit clustering for minimum delay and area.

Mehrdad Eslami Dehkordi, Stephen Dean Brown

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

2002

Incremental placement for layout driven optimizations on FPGAs.

Deshanand P. Singh, Stephen Dean Brown

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

The effect of cluster packing and node duplication control in delay driven clustering.

Mehrdad Eslami Dehkordi, Stephen Dean Brown

Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices.

Valavan Manohararajah, Terry P. Borer, Stephen Dean Brown, Zvonko G. Vranesic

Proceedings of the Field-Programmable Logic and Applications, 2002

Constrained clock shifting for field programmable gate arrays.

Deshanand P. Singh, Stephen Dean Brown

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

Integrated retiming and placement for field programmable gate arrays.

Deshanand P. Singh, Stephen Dean Brown

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

2001

The case for registered routing switches in field programmable gate arrays.

Deshanand P. Singh, Stephen Dean Brown

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001

2000

The NUMAchine Multiprocessor.

R. Grindley, Tarek S. Abdelrahman, Stephen Dean Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic

Proceedings of the 2000 International Conference on Parallel Processing, 2000

Technology mapping issues for an FPGA with lookup tables and PLA-like blocks.

Alireza Kaviani, Stephen Dean Brown

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

1999

The Hybrid Field-Programmable Architecture.

Alireza Kaviani, Stephen Dean Brown

IEEE Des. Test Comput., 1999

1998

An LPGA with Foldable PLA-style Logic Blocks.

Jason Helge Anderson, Stephen Dean Brown

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

Design and Implementation of the NUMAchine Multiprocessor.

A. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic

Proceedings of the 35th Conference on Design Automation, 1998

Technology Mapping for Large Complex PLDs.

Jason Helge Anderson, Stephen Dean Brown

Proceedings of the 35th Conference on Design Automation, 1998

Computational field programmable architecture.

Alireza Kaviani, Daniel Vranesic, Stephen Dean Brown

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1997

On two-step routing for FPGAS.

Guy G. Lemieux, Stephen Dean Brown, Daniel Vranesic

Proceedings of the 1997 International Symposium on Physical Design, 1997

1996

Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays.

Stephen Dean Brown, Muhammad M. Khellah, Guy Lemieux

VLSI Design, 1996

FPGA and CPLD Architectures: A Tutorial.

Stephen Dean Brown, Jonathan Rose

IEEE Des. Test Comput., 1996

Minimizing FPGA Interconnect Delays.

Stephen Dean Brown, Muhammad M. Khellah, Zvonko G. Vranesic

IEEE Des. Test Comput., 1996

FPGA Architectural Research: A Survey.

Stephen Dean Brown

IEEE Des. Test Comput., 1996

Hybrid FPGA Architecture.

Alireza Kaviani, Stephen Dean Brown

Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools.

Stephen Dean Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic

Proceedings of the 33st Conference on Design Automation, 1996

1993

A stochastic model to predict the routability of field-programmable gate arrays.

Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1992

A detailed router for field-programmable gate arrays.

Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Improving FPGA Routing Architectures Using Architecture and CAD Interactions.

Benjamin Tseng, Jonathan Rose, Stephen Dean Brown

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992