Joachim Knäblein

According to our database1, Joachim Knäblein authored at least 9 papers between 1999 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2013
MORPHEUS: A heterogeneous dynamically reconfigurable platform for designing highly complex embedded systems.
ACM Trans. Embed. Comput. Syst., 2013

2010
Technology Independent, Embedded Logic Cores Utilizing synthesizable embedded FPGA-cores for ASIC design validation.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010

Demonstration of an in-band reconfiguration data distribution and network node reconfiguration.
Proceedings of the Design, Automation and Test in Europe, 2010

An in-band reconfigurable network node based on a heterogeneous platform.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

2009
Testfallgenerierung für SystemC-Designs mit abstrakten Modellbeschreibungen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009

2008
Implementation of Parallel LFSR-based Applications on an Adaptive DSP featuring a Pipelined Configurable Gate Array.
Proceedings of the Design, Automation and Test in Europe, 2008

2006
Formal Verification of Abstract System and Protocol Specifications.
Proceedings of the 30th Annual IEEE / NASA Software Engineering Workshop (SEW-30 2006), 2006

Formale Spezifikation und Verifikation abstrakter Beschreibungen von Telekommunikationsprotokollen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

1999
Advanced Synchronous Scan Test Methodology for Multi Clock Domain ASICs.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999


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