Eric S. Chung

Orcid: 0000-0001-5871-4346

According to our database1, Eric S. Chung authored at least 33 papers between 2004 and 2023.

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Bibliography

2023
Microscaling Data Formats for Deep Learning.
CoRR, 2023

Shared Microexponents: A Little Shifting Goes a Long Way.
CoRR, 2023


2020
Pushing the Limits of Narrow Precision Inferencing at Cloud Scale with Microsoft Floating Point.
Proceedings of the Advances in Neural Information Processing Systems 33: Annual Conference on Neural Information Processing Systems 2020, 2020

2019
Inside Project Brainwave's Cloud-Scale, Real-Time AI Processor.
IEEE Micro, 2019

SysML: The New Frontier of Machine Learning Systems.
CoRR, 2019

2018
Serving DNNs in Real Time at Datacenter Scale with Project Brainwave.
IEEE Micro, 2018


A Configurable Cloud-Scale DNN Processor for Real-Time AI.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

2017
Configurable Clouds.
IEEE Micro, 2017

Deep Learning in the Enhanced Cloud.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

2016
A cloud-scale acceleration architecture.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016


2015
A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services.
IEEE Micro, 2015

Toward accelerating deep learning at scale using specialized hardware in the datacenter.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

2014
FPGA-Accelerated Simulation of Computer Systems
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01744-5, 2014

A High Memory Bandwidth FPGA Accelerator for Sparse Matrix-Vector Multiplication.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

2013
LINQits: big data on little clients.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

Cross-platform FPGA accelerator development using CoRAM and CONNECT.
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Towards automatic customization of interconnect and memory in the CoRAM abstraction (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

ShrinkWrap: Compiler-Enabled Optimization and Customization of Soft Memory Interconnects.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Reconfigurable computing in the era of post-silicon scaling [panel discussion].
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

2012
Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Towards a Universal FPGA Matrix-Vector Multiplication Architecture.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2011
CoRAM: an in-fabric memory architecture for FPGA-based computing.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010
High-Level Design and Validation of the BlueSPARC Multithreaded Processor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

2009
ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2009

Implementing a high-performance multithreaded microprocessor: A case study in high-level design and validation.
Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

2008
A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

2007
PROToFLEX: FPGA-accelerated Hybrid Functional Simulator.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

2005
TRUSS: A Reliable, Scalable Server Architecture.
IEEE Micro, 2005

2004
Development and evaluation of emerging design patterns for ubiquitous computing.
Proceedings of the Conference on Designing Interactive Systems: Processes, 2004


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