Jon Garlett

According to our database, Jon Garlett authored at least 5 papers between 2003 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology.

Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Troy J. Beukema, William R. Kelly, Hui H. Xu, David Freitas, Andrea Prati, Daniele Gardellini, Robert Reutemann, Giovanni Cervelli, Juergen Hertle, Matthew Baecher, Jon Garlett, Pier Andrea Francese, John F. Ewen, David Hanson, Daniel W. Storaska, Mounir Meghelli

IEEE J. Solid State Circuits, 2014

2012

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology.

John F. Bulzacchelli, Christian Menolfi, Troy J. Beukema, Daniel W. Storaska, Juergen Hertle, David Hanson, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William R. Kelly, L. R. Chieco, Glenn Ritter, J. A. Sorice, Jon Garlett, Robert Callan, Matthias Braendli, Peter Buchmann, Marcel A. Kossel, Thomas Toifl, Daniel J. Friedman

IEEE J. Solid State Circuits, 2012

A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology.

John F. Bulzacchelli, Troy J. Beukema, Daniel W. Storaska, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Christian Menolfi, David Hanson, Juergen Hertle, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William R. Kelly, Glenn Ritter, Jon Garlett, Robert Callan, Thomas Toifl, Daniel J. Friedman

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology.

Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Sergey V. Rylov, Troy J. Beukema, David Freitas, William R. Kelly, Michael Shannon, Jieming Qi, Hui H. Xu, Joseph Natonio, Todd M. Rasmus, Jong-Ru Guo, Michael Wielgos, Jon Garlett, Michael Sorna, Mounir Meghelli

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2003

In-system failure investigation on 0.18 μm high speed serial link ASIC using logic built-in self test.

Jeanne Trinko Mechler, Raymond J. Bulaga, Jon Garlett

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003