Kamran Zarrineh

According to our database1, Kamran Zarrineh authored at least 18 papers between 1996 and 2011.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2011
Feedback based droop mitigation.
Proceedings of the Design, Automation and Test in Europe, 2011

2008
Design for Test Challenges of High Performance/Low Power Microprocessors.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2005
Design and analysis of multiple weight linear compactors of responses containing unknown values.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2003
The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2001
Automatic generation and compaction of March tests for memory arrays.
IEEE Trans. Very Large Scale Integr. Syst., 2001

System-on-Chip Testability Using LSSD Scan Structures.
IEEE Des. Test Comput., 2001

Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Defect Analysis and a New Fault Model for Multi-port SRAMs.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories.
Proceedings of the 8th IEEE International Workshop on Memory Technology, 2000

Self test architecture for testing complex memory structures.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999
A New Framework For Automatic Generation, Insertion and Verification of Memory Built-In Self Test Units.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

A design for test perspective on memory synthesis.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Programmable Memory BIST and a New Synthesis Framework.
Proceedings of the Digest of Papers: FTCS-29, 1999

On Programmable Memory Built-In Self Test Architectures.
Proceedings of the 1999 Design, 1999

1998
Automatic Insertion of Scan Structures to Enhance Testability of Embedded Memories, Cores and Chips.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

A new framework for generating optimal March tests for memory arrays.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997
Addressing Early Design-For-Test Synthesis in a Production Environment.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996
A Design For Test Perspective on I/O Management.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996


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