Adelio Salsano

According to our database1, Adelio Salsano authored at least 47 papers between 1993 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2012
Optimized Implementation of RNS FIR Filters Based on FPGAs.
J. Signal Process. Syst., 2012

On the use of Karatsuba formula to detect errors in GF((2(sup)n(/sup))(sup)2(/sup)) multipliers.
IET Circuits Devices Syst., 2012

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011
Feedback based droop mitigation.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
High throughput and low power dissipation in QCA pipelines using Bennett clocking.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Error Detection and Correction in Content Addressable Memories.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009
Error detection in addition chain based ECC Point Multiplication.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Error Correction Codes for SEU and SEFI Tolerant Memory Systems.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008
Guest Editorial.
J. Electron. Test., 2008

Analysis and Evaluations of Reliability of Reconfigurable FPGAs.
J. Electron. Test., 2008

Totally Fault Tolerant RNS Based FIR Filters.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

On the use of signed digit arithmetic for the new 6-inputs LUT based FPGAs.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A Novel Error Detection and Correction Technique for RNS Based FIR Filters.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007
Concurrent Error Detection in Reed-Solomon Encoders and Decoders.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Analysis of Errors and Erasures in Parity Sharing RS Codecs.
IEEE Trans. Computers, 2007

Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Optimization of Self Checking FIR filters by means of Fault Injection Analysis.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006
Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders.
IEEE Trans. Computers, 2006

Fault tolerant design of signed digit based FIR filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Concurrent error detection in Reed Solomon decoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Localization of Faults in Radix-n Signed Digit Adders.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Reliability Evaluation of Repairable/Reconfigurable FPGAs.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded Microcontrollers.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005
Sufficient Conditions to Impose Derivative Constraints on MISO Takagi-Sugeno Fuzzy Logic Systems.
IEEE Trans. Fuzzy Syst., 2005

A Comparative Evaluation of Designs for Reliable Memory Systems.
J. Electron. Test., 2005

Design of a QCA Memory with Parallel Read/Serial Write.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Design of a Self Checking Reed Solomon Encoder.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

FPGA oriented design of parity sharing RS codecs.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

A Self Checking Reed Solomon Encoder: Design and Analysis.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories.
Proceedings of the 2005 Design, 2005

2004
High spectral purity digital direct synthesizer implementation by means of a fuzzy approximator.
Appl. Soft Comput., 2004

A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Data Integrity Evaluations of Reed Solomon Codes for Storage Systems.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Monitoring Methodology for TID Damaging of SDRAM Devices based on Retention Time Analysis.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

2003
Design of a fault tolerant solid state mass memory.
IEEE Trans. Reliab., 2003

A fault tolerant hardware based file system manager for solid state mass memory.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Error Detection in Signed Digit Arithmetic Circuit with Parity Checker.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002
A self-checking cell logic block for fault tolerant FPGAs.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Development of a dynamic routing system for a fault tolerant solid state mass memory.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Noise estimation in digital images using fuzzy processing.
Proceedings of the 2001 International Conference on Image Processing, 2001

System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
Development of an evaluation model for the design of fault-tolerant solid state mass memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A Fault-Tolerant 176 Gbit Solid State Mass Memory Architecture.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

1999
Design of Fault-Tolerant Solid State Mass Memory.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Failure Tests on 64 Mb SDRAM in Radiation Environment.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

1993
A High Speed Reed-Solomon Encoder-Decoder for Fault Tolerant Solid State Disks.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993


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