Shin-Rung Wu

According to our database, Shin-Rung Wu authored at least 4 papers between 2015 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update.

Haruki Mori, Wei-Chang Zhao, Cheng-En Lee, Chia-Fu Lee, Yu-Hao Hsu, Chao-Kai Chuang, Takeshi Hashizume, Hao-Chun Tung, Yao-Yi Liu, Shin-Rung Wu, Kerem Akarvardar, Tan-Li Chou, Hidehiro Fujiwara, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2021

A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue.

Hidehiro Fujiwara, Yi-Hsin Nien, Chih-Yu Lin, Hsien-Yu Pan, Hao-Wen Hsu, Shin-Rung Wu, Yao-Yi Liu, Yen-Huei Chen, Hung-Jen Liao, Jonathan Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2016

A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications.

Hidehiro Fujiwara, Yen-Huei Chen, Chih-Yu Lin, Wei-Cheng Wu, Dar Sun, Shin-Rung Wu, Hung-Jen Liao, Jonathan Chang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies.

Hidehiro Fujiwara, Li-Wen Wang, Yen-Huei Chen, Kao-Cheng Lin, Dar Sun, Shin-Rung Wu, Jhon-Jhy Liaw, Chih-Yung Lin, Mu-Chi Chiang, Hung-Jen Liao, Shien-Yang Wu, Jonathan Chang

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015