Dar Sun

According to our database1, Dar Sun authored at least 7 papers between 2012 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
A 5-nm 254-TOPS/W 221-TOPS/mm<sup>2</sup> Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021
A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS.
IEEE J. Solid State Circuits, 2021

An 89TOPS/W and 16.3TOPS/mm<sup>2</sup> All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2016
A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2012
Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM.
IEEE J. Solid State Circuits, 2012


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