Konstantinos Tatas
Orcid: 0000-0001-5087-5778Affiliations:
- Frederick University, Department of Computer Science and Engineering, Nicosia, Cyprus
According to our database1,
Konstantinos Tatas
authored at least 41 papers
between 2000 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
A Low-Cost Real-Time Cyber Physical System for Overcoming Excess Braking Issues In Race Cars.
Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023
2021
Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021
Towards an Analytical Model of Latency in Deflection Routing: A Stochastic Process Approach for Bufferless NoCs.
Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021
2020
J. Intell. Fuzzy Syst., 2020
2018
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018
Towards Dynamic Multi-task Schedulling of OpenCL Programs on Emerging CPU-GPU-FPGA Heterogeneous Platforms: A Fuzzy Logic Approach.
Proceedings of the 2018 IEEE International Conference on Cloud Computing Technology and Science, 2018
2017
Microprocess. Microsystems, 2017
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
2016
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016
2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
2013
Int. J. Adapt. Resilient Auton. Syst., 2013
2012
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012
Proceedings of the 2nd Baltic Congress on Future Internet Communications, 2012
2008
Rapid Prototyping of the Data-Driven Chip-Multiprocessor (d<sup>2</sup>-CMP) Using FPGAs.
Parallel Process. Lett., 2008
2007
Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications.
Integr., 2007
2006
Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors.
J. VLSI Signal Process., 2006
Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
A novel methodology for designing high-performance and low-energy FPGA routing architecture.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006
2005
A complete platform and toolset for system implementation on fine-grain reconfigurable hardware.
Microprocess. Microsystems, 2005
Memory power optimization of hardware implementations of multimedia applications onto FPGA platforms.
J. Embed. Comput., 2005
J. Circuits Syst. Comput., 2005
A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications.
IEICE Trans. Inf. Syst., 2005
DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004
Proceedings of the Field Programmable Logic and Application, 2004
2003
Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms.
Real Time Imaging, 2003
Proceedings of the Integrated Circuit and System Design, 2003
Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms.
Proceedings of the Integrated Circuit and System Design, 2003
A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations.
Proceedings of the Field-Programmable Logic and Applications, 2002
2001
Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
Power, performance and area exploration of block matching algorithms mapped on programmable processors.
Proceedings of the 2001 International Conference on Image Processing, 2001
Data and instruction memory exploration of embedded systems for multimedia applications.
Proceedings of the IEEE International Conference on Acoustics, 2001
2000
Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications.
Proceedings of the Integrated Circuit Design, 2000