Alexandros Bartzas
According to our database1,
Alexandros Bartzas
authored at least 41 papers
between 2006 and 2020.
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Bibliography
2020
Proceedings of the 17th International Conference on Information Systems for Crisis Response and Management, 2020
2016
Improving Dynamic Memory Allocation on Many-Core Embedded Systems With Distributed Shared Memory.
IEEE Embed. Syst. Lett., 2016
2015
Placement of Linked Dynamic Data Structures over Heterogeneous Memories in Embedded Systems.
ACM Trans. Embed. Comput. Syst., 2015
Using Chaos Theory based workload analysis to perform Dynamic Frequency Scaling on MPSoCs.
J. Syst. Archit., 2015
2013
ACM Trans. Embed. Comput. Syst., 2013
System scenarios-based architecture level exploration of SDR application using a network-on-chip simulation framework.
Microprocess. Microsystems, 2013
Int. J. Adapt. Resilient Auton. Syst., 2013
SWAN-iCare: A smart wearable and autonomous negative pressure device for wound monitoring and therapy.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013
Distributed run-time resource management for malleable applications on many-core platforms.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
Des. Autom. Embed. Syst., 2012
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
Parallel paradigms and run-time management techniques for many-core architectures: the 2PARMA approach.
Proceedings of the 2012 Interconnection Network Architecture, 2012
A Methodology for Efficient Use of OpenCL, ESL and FPGAs in Multi-core Architectures.
Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012
A divide and conquer based distributed run-time mapping methodology for many-core platforms.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012
Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012
2011
Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations.
IEEE Embed. Syst. Lett., 2011
Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Runtime Tuning of Dynamic Memory Management For Mitigating Footprint-Fragmentation Variations.
Proceedings of the ARCS 2011, 2011
2010
Software metadata: Systematic characterization of the memory behaviour of dynamic applications.
J. Syst. Softw., 2010
Custom multi-threaded Dynamic Memory Management for Multiprocessor System-on-Chip platforms.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010
2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms.
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the ARCS '10, 2010
Proceedings of the ARCS '10, 2010
2009
Direct memory access usage optimization in network applications for reduced memory latency and energy consumption.
J. Embed. Comput., 2009
J. Embed. Comput., 2009
Multi-granularity NoC Simulation Framework for Early Phase Exploration of SDR Hardware Platforms.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the 16th International Conference on Digital Signal Processing, 2009
2008
Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology.
Int. J. Reconfigurable Comput., 2008
Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
Systematic methodology for exploration of performance - Energy trade-offs in network applications using Dynamic Data Type refinement.
J. Syst. Archit., 2007
Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
2006
Systematic design flow for dynamic data management in visual texture decoder of MPEG-4.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006