Shuso Fujii

According to our database1, Shuso Fujii authored at least 9 papers between 2004 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2012
An Embedded DRAM Technology for High-Performance NAND Flash Memories.
IEEE J. Solid State Circuits, 2012

2011
A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs.
IEEE J. Solid State Circuits, 2011

A 128 Mb Chain FeRAM and System Design for HDD Application and Enhanced HDD Performance.
IEEE J. Solid State Circuits, 2011

2010
A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode.
IEEE Trans. Very Large Scale Integr. Syst., 2010

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes.
IEEE J. Solid State Circuits, 2010


2009

2006
A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2004
Post-Packaging Auto Repair Techniques for Fast Row Cycle Embedded DRAM.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004


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