Ryu Ogiwara

According to our database1, Ryu Ogiwara authored at least 10 papers between 2000 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs.
IEEE J. Solid State Circuits, 2015

2011
A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs.
IEEE J. Solid State Circuits, 2011

2010
A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode.
IEEE Trans. Very Large Scale Integr. Syst., 2010

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes.
IEEE J. Solid State Circuits, 2010


2009

2006
A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2003
A 32-Mb chain FeRAM with segment/stitch array architecture.
IEEE J. Solid State Circuits, 2003

2001
A 76-mm<sup>2</sup> 8-Mb chain ferroelectric memory.
IEEE J. Solid State Circuits, 2001

2000
A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor.
IEEE J. Solid State Circuits, 2000


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