Kubilay Atasu

According to our database1, Kubilay Atasu authored at least 39 papers between 2003 and 2020.

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Bibliography

2020
Many-Core Clique Enumeration with Fast Set Intersections.
Proc. VLDB Endow., 2020

Tera-scale coordinate descent on GPUs.
Future Gener. Comput. Syst., 2020

Parallelizing Maximal Clique Enumeration on Modern Manycore Processors.
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

2019
Addressing Interpretability and Cold-Start in Matrix Factorization for Recommender Systems.
IEEE Trans. Knowl. Data Eng., 2019

Linear-Complexity Data-Parallel Earth Mover's Distance Approximations.
Proceedings of the 36th International Conference on Machine Learning, 2019

2018
A hardware compilation framework for text analytics queries.
J. Parallel Distributed Comput., 2018

Faster Text Similarity Using a Linear-Complexity Relaxed Word Mover's Distance.
ERCIM News, 2018

Low-Complexity Data-Parallel Earth Mover's Distance Approximations.
CoRR, 2018

2017
Foreword to the Special Section on Reconfigurable Computing.
J. Signal Process. Syst., 2017

Large-Scale Stochastic Learning Using GPUs.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

High-Performance Recommender System Training Using Co-Clustering on CPU/GPU Clusters.
Proceedings of the 46th International Conference on Parallel Processing, 2017

Understanding and optimizing the performance of distributed machine learning applications on apache spark.
Proceedings of the 2017 IEEE International Conference on Big Data, BigData 2017, 2017

Linear-complexity relaxed word Mover's distance with GPU acceleration.
Proceedings of the 2017 IEEE International Conference on Big Data, BigData 2017, 2017

2016
Feature-rich Regular Expression Matching Accelerator for Text Analytics.
J. Signal Process. Syst., 2016

High-Performance Distributed Machine Learning using Apache SPARK.
CoRR, 2016

Annotation-based finite-state transducers on reconfigurable devices.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015
Leftmost longest regular expression matching in reconfigurable logic.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

2014
Guest Editorial: Application Specific Processors and Architectures.
J. Signal Process. Syst., 2014

Giving Text Analytics a Boost.
IEEE Micro, 2014

Hardware-accelerated text analytics.
Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

Compiling text analytics queries to FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Resource-efficient regular expression matching architecture for text analytics.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013
Exploring the design space of programmable regular expression matching accelerators.
J. Syst. Archit., 2013

Hardware-Accelerated Regular Expression Matching with Overlap Handling on IBM PowerEN Processor.
Proceedings of the 27th IEEE International Symposium on Parallel and Distributed Processing, 2013

Token-based dictionary pattern matching for text analytics.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Hardware-accelerated regular expression matching for high-throughput text analytics.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
Complexity of Computing Convex Subgraphs in Custom Instruction Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2012

FISH: Fast Instruction SyntHesis for Custom Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Designing a Programmable Wire-Speed Regular-Expression Matching Accelerator.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Proving correctness of regular expression accelerators.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2009
Memory-efficient distribution of regular expressions for fast deep packet inspection.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008
CHIPS: Custom Hardware Instruction Processor Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Fast custom instruction identification by convex subgraph enumeration.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007
Optimizing instruction-set extensible processors under data bandwidth constraints.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Exact and approximate algorithms for the extension of embedded processor instruction sets.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2005
An integer linear programming approach for identifying instruction-set extensions.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

2004
Efficient AES implementations for ARM based platforms.
Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004

Introduction of local memory elements in instruction set extensions.
Proceedings of the 41th Design Automation Conference, 2004

2003
Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints.
Int. J. Parallel Program., 2003


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