Laurent Lopez

According to our database1, Laurent Lopez authored at least 9 papers between 2005 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2015
Improvement of MOSFET matching characterization with calibrated multiplexed test structure.
Microelectron. Reliab., 2015

Dynamic current reduction of CMOS digital circuits through design and process optimization.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

Layout optimizations to decrease internal power and area in digital CMOS standard cells.
Proceedings of the 38th International Convention on Information and Communication Technology, 2015

2014
Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2013
Effect of ions presence in the SiOCH inter metal dielectric structure.
Proceedings of the European Solid-State Device Research Conference, 2013

2011
Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress.
Microelectron. Reliab., 2011

Temperature and hump effect impact on output voltage spread of low power bandgap designed in the sub-threshold area.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2007
A new method to quantify retention-failed cells of an EEPROM CAST.
Microelectron. Reliab., 2007

2005
A New Embedded Measurement Structure for eDRAM Capacitor.
Proceedings of the 2005 Design, 2005


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