Jean-Luc Ogier
According to our database1,
Jean-Luc Ogier
authored at least 14 papers
between 2007 and 2017.
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Bibliography
2017
Physically-based evaluation of aging contributions in HC/FN-programmed 40 nm NOR Flash technology.
Microelectron. Reliab., 2017
2014
Impact of endurance degradation on the programming efficiency and the energy consumption of NOR flash memories.
Microelectron. Reliab., 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
2013
Microelectron. Reliab., 2013
Proceedings of the European Solid-State Device Research Conference, 2013
2012
Investigation of the effects of constant voltage stress on thin SiO<sub>2</sub> layers using dynamic measurement protocols.
Microelectron. Reliab., 2012
Effects of Lightly Doped Drain and Channel Doping Variations on Flash Memory Performances and Reliability.
J. Low Power Electron., 2012
2011
Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress.
Microelectron. Reliab., 2011
2009
Influence of various process steps on the reliability of PMOSFETs submitted to negative bias temperature instabilities.
Microelectron. Reliab., 2009
2008
Dynamic stress method for accurate NVM oxide robustness evaluation for automotive applications.
Microelectron. Reliab., 2008
Assessment of temperature and voltage accelerating factors for 2.3-3.2 nm SiO<sub>2</sub> thin oxides stressed to hard breakdown.
Microelectron. Reliab., 2008
2007
Microelectron. Reliab., 2007
A comprehensive study of stress induced leakage current using a floating gate structure for direct applications in EEPROM memories.
Microelectron. Reliab., 2007
Oxide reliability below 3 nm for advanced CMOS: Issues, characterization, and solutions.
Microelectron. Reliab., 2007