Lucas Morais

According to our database, Lucas Morais authored at least 6 papers between 2016 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2025

Boosting Task Scheduling Data Locality with Low-latency, HW-accelerated Label Propagation.

Lucas Morais, Juan Miguel De Haro Ruiz, Alfredo Goldman, Guido Araujo, Giacomo Pedretti, Jim Ignowski, Michael Frank, Xavier Martorell, Daniel Jiménez-González, Carlos Álvarez

Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture, 2025

2024

Enabling HW-Based Task Scheduling in Large Multicore Architectures.

Lucas Morais, Carlos Álvarez, Daniel Jiménez-González, Juan Miguel De Haro Ruiz, Guido Araujo, Michael Frank, Alfredo Goldman, Xavier Martorell

IEEE Trans. Computers, January, 2024

The TEXTAROSSA Project: Cool all the Way Down to the Hardware.

Antonio Filgueras, Giovanni Agosta, Marco Aldinucci, Carlos Álvarez, Pasqua D'Ambra, Massimo Bernaschi, Andrea Biagioni, Daniele Cattaneo, Alessandro Celestini, Massimo Celino, Carlotta Chiarini, Francesca Lo Cicero, Paolo Cretaro, William Fornaciari, Ottorino Frezza, Andrea Galimberti, Francesco Giacomini, Juan Miguel De Haro Ruiz, Francesco Iannone, Daniel Jaschke, Daniel Jiménez-González, Michal Kulczewski, Alberto Leva, Alessandro Lonardo, Michele Martinelli, Xavier Martorell, Simone Montangero, Lucas Morais, Ariel Oleksiak, Paolo Palazzari, Luca Pontisso, Federico Reghenzani, Cristian Rossi, Sergio Saponara, Carlo Saverio Lodi, Francesco Simula, Federico Terraneo, Piero Vicini, Miquel Vidal, Davide Zoni, Giuseppe Zummo

Proceedings of the 27th Euromicro Conference on Digital System Design, 2024

2022

Algorithms for Freight Train Scheduling.

Lucas Morais, Rodrigo Gonçalves, Alexandre Tazoniero, Fernando A. C. Gomide

Proceedings of the 14th International Joint Conference on Computational Intelligence, 2022

2019

Adding Tightly-Integrated Task Scheduling Acceleration to a RISC-V Multi-core Processor.

Lucas Morais, Vitor Silva, Alfredo Goldman, Carlos Álvarez, Jaume Bosch, Michael Frank, Guido Araujo

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

2016

Task parallel programming model + hardware acceleration = performance advantage.

Tamer Dallou, Divino Cesar Soares Lucas, Guido Araujo, Lucas Morais, Eduardo Ferreira Barbosa, Michael Frank, Richard Bagley, Raj Sayana

Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016