Andrea Galimberti

Orcid: 0000-0003-0254-3933

According to our database1, Andrea Galimberti authored at least 25 papers between 2000 and 2023.

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Bibliography

2023
Design and implementation of a QC-MDPC code-based post-quantum KEM targeting FPGAs
PhD thesis, 2023

A Survey on Run-time Power Monitors at the Edge.
ACM Comput. Surv., 2023


HLS-based acceleration of the BIKE post-quantum KEM on embedded-class heterogeneous SoCs.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

An Evaluation of the State-Of-The-Art Software and Hardware Implementations of BIKE.
Proceedings of the 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2023

Hardware and Software Support for Mixed Precision Computing: a Roadmap for Embedded and HPC Systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Towards EXtreme scale technologies and accelerators for euROhpc hw/Sw supercomputing applications for exascale: The TEXTAROSSA approach.
Microprocess. Microsystems, November, 2022

Efficient and Scalable FPGA Design of GF($2^m$2m) Inversion for Post-Quantum Cryptosystems.
IEEE Trans. Computers, 2022

Cost-effective fixed-point hardware support for RISC-V embedded systems.
J. Syst. Archit., 2022

On the Effectiveness of True Random Number Generators Implemented on FPGAs.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022

Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

FPGA implementation of BIKE for quantum-resistant TLS.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

On the use of hardware accelerators in QC-MDPC code-based cryptography.
Proceedings of the CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17, 2022

2021
An FPU design template to optimize the accuracy-efficiency-area trade-off.
Sustain. Comput. Informatics Syst., 2021


2020
Efficient and Scalable FPGA-Oriented Design of QC-LDPC Bit-Flipping Decoders for Post-Quantum Cryptography.
IEEE Access, 2020

Flexible and Scalable FPGA-Oriented Design of Multipliers for Large Binary Polynomials.
IEEE Access, 2020

VGM-Bench: FPU Benchmark Suite for Computer Vision, Computer Graphics and Machine Learning Applications.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020

2019
Evaluating the Trade-offs in the Hardware Design of the LEDAcrypt Encryption Functions.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Probabilistic-WCET Reliability: On the experimental validation of EVT hypotheses.
Proceedings of the International Conference on Omni-Layer Intelligent Systems, 2019

2018
SOON: Supporting the Evaluation of Researchers' Profiles.
Proceedings of the Knowledge Management in Organizations - 13th International Conference, 2018

A Classifier to Identify Soft Skills in a Researcher Textual Description.
Proceedings of the Applications of Evolutionary Computation, 2018

Back to the future: resource management in post-cloud solutions.
Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018

2010
DNA barcoding: a six-question tour to improve users' awareness about the method.
Briefings Bioinform., 2010

2000
A 3D Graphic Environment for Garments Design.
Proceedings of the From Geometric Modeling to Shape Modeling, 2000


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