Paolo Palazzari

Orcid: 0009-0003-2569-263X

According to our database1, Paolo Palazzari authored at least 46 papers between 1993 and 2023.

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Bibliography

2023
A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures.
CoRR, 2023

FastFlow targeting FPGAs.
Proceedings of the 31st Euromicro International Conference on Parallel, 2023

2022
Towards EXtreme scale technologies and accelerators for euROhpc hw/Sw supercomputing applications for exascale: The TEXTAROSSA approach.
Microprocess. Microsystems, November, 2022

2021

2020
Using High-Level Synthesis to Implement the Matrix-Vector Multiplication on FPGA.
Proceedings of the High Performance Computing - 35th International Conference, 2020

2018
Accelerating Key In-memory Database Functionality with FPGA Technology.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

2012
Effort, resources, and abstraction vs performance in high-level synthesis: finding new answers to an old question.
SIGARCH Comput. Archit. News, 2012

2010
Using ontologies for the federated simulation of critical infrastructures.
Proceedings of the International Conference on Computational Science, 2010

An ontological approach to simulate critical infrastructures.
J. Comput. Sci., 2010

Ontological Framework to Model Critical Infrastructures and their Interdependencies.
Proceedings of the Complexity in Engineering, 2010

2008
OpenFPGA CoreLib core library interoperability effort.
Parallel Comput., 2008

2007
The HARWEST High Level Synthesis Flow to Design a Special-Purpose Architecture to Simulate the 3D Ising Model.
Proceedings of the Parallel Computing: Architectures, 2007

2005
Statistical Methods for the Discovery of Co-Operative Transcription Factors: The Co-bind Code Revised.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

A Parallel Variable-Mesh FDTD Algorithm for the Solution of Large Electromagnetic Problems.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2004
A specialized hardware device for the protein similarity search.
Concurr. Pract. Exp., 2004

Synthesis of Pipelined Systems for the Contemporaneous Execution of Periodic and Aperiodic Tasks with Hard Real-Time Constraints.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

2003
Designing hardware for protein sequence analysis.
Bioinform., 2003

PROSIDIS: A Special Purpose Processor for PROtein SImilarity DIScovery.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

2002
LICO: A Multi-platform Channel-Based Communication Library.
Proceedings of the Recent Advances in Parallel Virtual Machine and Message Passing Interface, 9th European PVM/MPI Users' Group Meeting, Linz, Austria, September 29, 2002

High Level Synthesis for Programmable Devices: The HADES Project.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

2001
Hyper-systolic matrix multiplication.
Parallel Comput., 2001

Parallel dedicated hardware devices for heterogeneous computations.
Proceedings of the 2001 ACM/IEEE conference on Supercomputing, 2001

Parallel Simulation of Radio-Base Antennas on Massively Parallel Systems.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

2000
Automatic Mapping of System of N-Dimensional Affine Precurrence Equations (SARE) onto Distributed Memory Parallel Systems.
IEEE Trans. Software Eng., 2000

Automatic Generation of Parallel Programs from Affine Iterative Algorithms.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

Near-Field Numerical Characterization of Radio-Base Antennas with Parallel Electromagnetic Codes.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

The toroidal neural networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

High Level Software Synthesis of Affine Iterative Algorithms onto Parallel Architectures.
Proceedings of the High-Performance Computing and Networking, 8th International Conference, 2000

Heterogeneity as Key Feature of High Performance Computing: the PQE1 Prototype.
Proceedings of the 9th Heterogeneous Computing Workshop, 2000

1999
Massively parallel processing approach to fractal image compression with near-optimal coefficient quantization.
J. Syst. Archit., 1999

Performances of hole based, chaotic and minimal fully-adaptive routing algorithms under constant resource constraint.
Proceedings of the Parallel Computing: Fundamentals & Applications, 1999

Nonlinear image processing through sequences of fast cellular neural networks (FCNN).
Proceedings of the IEEE-EURASIP Workshop on Nonlinear Signal and Image Processing (NSIP'99), 1999

A New Memory-Saving Technique to Map System of Affine Recurrence Equations (SARE) onto Distributed Memory Systems.
Proceedings of the 13th International Parallel Processing Symposium / 10th Symposium on Parallel and Distributed Processing (IPPS / SPDP '99), 1999

1998
Virtual cut-through implementation of the HB packet switching routing algorithm.
Proceedings of the Sixth Euromicro Workshop on Parallel and Distributed Processing, 1998

Hyper-Systolic Implementation of BLAS-3 Routines on the APE100/Quadrics Machine.
Proceedings of the Applied Parallel Computing, 1998

Simulation of Patch Array Antennas through the Implementation of Finite-Difference Time-Domain (FD-TD) Algorithm on Distributed Memory Massively Parallel Systems.
Proceedings of the High-Performance Computing and Networking, 1998

1997
Automatic Template Generation for Solving n<sup>2</sup>-Problems on Parallel Systems with Arbitrary Topology.
Proceedings of the International Symposium on Software Engineering for Parallel and Distributed Systems, 1997

Hyper-Systolic Routing for SIMD Systems.
Proceedings of the Parallel Computing: Fundamentals, 1997

1996
Real time pipelined system design through simulated annealing.
J. Syst. Archit., 1996

Load Balancing with Internode Precedence Relations: A New Method for Static Allocation of DAGs into Parallel Systems.
Proceedings of the 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), 1996

A New Crossover Operator for Genetic Algorithms.
Proceedings of 1996 IEEE International Conference on Evolutionary Computation, 1996

1995
An adaptive deadlock and livelock free routing algorithm.
Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing (PDP '95), 1995

Global execution time minimization by allocating tasks in parallel systems.
Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing (PDP '95), 1995

Building the Fitness Function of a Genetic Algorithm through Straight Simulation: Application to Search for Parameters of a Policing Algorithm in ATM Environment.
Proceedings of the EUROSIM'96, 1995

A new method for optimization of allocation and scheduling in real time applications.
Proceedings of the 7th Euromicro Workshop on Real-Time Systems, 1995

1993
Data flow graphs granularity for overhead reduction within a PE in multiprocessor systems.
Proceedings of the International Conference on Application-Specific Array Processors, 1993


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