Davide Zoni

According to our database1, Davide Zoni authored at least 44 papers between 2012 and 2021.

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Bibliography

2021
An FPU design template to optimize the accuracy-efficiency-area trade-off.
Sustain. Comput. Informatics Syst., 2021

Automatic identification and hardware implementation of a resource-constrained power model for embedded systems.
Sustain. Comput. Informatics Syst., 2021

2020
Scramble Suit: A Profile Differentiation Countermeasure to Prevent Template Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

All-Digital Control-Theoretic Scheme to Optimize Energy Budget and Allocation in Multi-Cores.
IEEE Trans. Computers, 2020

All-Digital Energy-Constrained Controller for General-Purpose Accelerators and CPUs.
IEEE Embed. Syst. Lett., 2020

Efficient and Scalable FPGA-Oriented Design of QC-LDPC Bit-Flipping Decoders for Post-Quantum Cryptography.
IEEE Access, 2020

Flexible and Scalable FPGA-Oriented Design of Multipliers for Large Binary Polynomials.
IEEE Access, 2020

VGM-Bench: FPU Benchmark Suite for Computer Vision, Computer Graphics and Machine Learning Applications.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020

Integrating Side Channel Security in the FPGA Hardware Design Flow.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2020

2019
Analysis and countermeasures to side-channel attacks: a hardware design perspective.
Proceedings of the 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2019

Partial Packet Forwarding to Improve Performance in Fully Adaptive Routing for Cache-Coherent NoCs.
Proceedings of the 27th Euromicro International Conference on Parallel, 2019

Evaluating the Trade-offs in the Hardware Design of the LEDAcrypt Encryption Functions.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018
A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture.
ACM Trans. Design Autom. Electr. Syst., 2018

DarkCache: Energy-Performance Optimization of Tiled Multi-Cores by Adaptively Power-Gating LLC Banks.
ACM Trans. Archit. Code Optim., 2018

PowerTap: All-digital power meter modeling for run-time power monitoring.
Microprocess. Microsystems, 2018

Exploring manycore architectures for next-generation HPC systems through the MANGO approach.
Microprocess. Microsystems, 2018

Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

Fast Estimations of Failure Probability Over Long Time Spans.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

PowerProbe: Run-time power modeling through automatic RTL instrumentation.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Towards Fine-Grained DVFS in Embedded Multi-core CPUs.
Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018

2017
CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties.
Microprocess. Microsystems, 2017

BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers.
J. Parallel Distributed Comput., 2017

DENA: A DVFS-Capable Heterogeneous NoC Architecture.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017


2016
A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations.
J. Signal Process. Syst., 2016

CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-Based NoCs.
IEEE Trans. Parallel Distributed Syst., 2016

Enabling HPC for QoS-sensitive applications: The MANGO approach.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
A control-based methodology for power-performance optimization in NoCs exploiting DVFS.
J. Syst. Archit., 2015

Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators.
ACM J. Emerg. Technol. Comput. Syst., 2015

An accurate simulation framework for thermal explorations and optimizations.
Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2015

TEST: Assessing NoC Policies Facing Aging and Leakage Power.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

The MANGO FET-HPC Project: An Overview.
Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015

2013
An analytical, dynamic, power-performance router model for run-time NoC optimizations.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

Adaptive routing and Dynamic Frequency Scaling for NoC power-performance optimizations.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

A cycle accurate simulation framework for asynchronous NoC design.
Proceedings of the 2013 International Symposium on System on Chip, 2013

NBTI-aware design of NoC buffers.
Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip, 2013

Sensor-wise methodology to face NBTI stress of NoC buffers.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
A sensor-less NBTI mitigation methodology for NoC architectures.
Proceedings of the IEEE 25th International SOC Conference, 2012

Towards energy-efficient functional configuration in WSNs.
Proceedings of the 11th IFAC Conference on Programmable Devices and Embedded Systems, 2012

A Temperature and Reliability Oriented Simulation Framework for Multi-core Architectures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Thermal/performance trade-off in network-on-chip architectures.
Proceedings of the 2012 International Symposium on System on Chip, 2012

HANDS: heterogeneous architectures and networks-on-chip design and simulation.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Consolidation of multi-tier workloads with performance and reliability constraints.
Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012

A Low-Overhead Heuristic for Mixed Workload Resource Partitioning in Cluster-Based Architectures.
Proceedings of the Architecture of Computing Systems - ARCS 2012 - 25th International Conference, Munich, Germany, February 28, 2012


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