Makarand Shirasgaonkar

According to our database1, Makarand Shirasgaonkar authored at least 4 papers between 2012 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2015
A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology.
IEEE J. Solid State Circuits, 2015

2014
An Adaptive Body-Biased Clock Generation System in 28nm CMOS.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering.
Proceedings of the Symposium on VLSI Circuits, 2014

2012
A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012


  Loading...