Adam Chou

According to our database1, Adam Chou authored at least 7 papers between 2014 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET.
IEEE J. Solid State Circuits, 2021

2020
6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2018
A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2017
A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET.
IEEE J. Solid State Circuits, 2017

6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2015
A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology.
IEEE J. Solid State Circuits, 2015

2014
A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering.
Proceedings of the Symposium on VLSI Circuits, 2014


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