Fred Heaton

According to our database1, Fred Heaton authored at least 7 papers between 2007 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology.
IEEE J. Solid State Circuits, 2015

2014
A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems.
IEEE J. Solid State Circuits, 2014

A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering.
Proceedings of the Symposium on VLSI Circuits, 2014

2013
A 6.4Gb/s near-ground single-ended transceiver for dual-rank DIMM memory interface systems.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2010
A 32mW 7.4Gb/s protocol-agile source-series-terminated transmitter in 45nm CMOS SOI.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2007
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007


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