Marco Bertuletti

Orcid: 0000-0001-7576-0803

According to our database1, Marco Bertuletti authored at least 14 papers between 2023 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
A 66-Gb/s/5.5-W RISC-V Many-Core Cluster for 5G+ Software-Defined Radio Uplinks.
IEEE Trans. Very Large Scale Integr. Syst., August, 2025

TeraNoC: A Multi-Channel 32-bit Fine-Grained, Hybrid Mesh-Crossbar NoC for Efficient Scale-up of 1000+ Core Shared-L1-Memory Clusters.
CoRR, August, 2025

MemPool Flavors: Between Versatility and Specialization in a RISC-V Manycore Cluster.
CoRR, April, 2025

Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing.
CoRR, March, 2025

Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC.
IEEE Trans. Very Large Scale Integr. Syst., February, 2025

Optimizing Scalable Multi-Cluster Architectures for Next-Generation Wireless Sensing and Communication.
Proceedings of the 10th International Workshop on Advances in Sensors and Interfaces, 2025

TCDM Burst Access: Breaking the Bandwidth Barrier in Shared-L1 RVV Clusters Beyond 1000 FPUs.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications.
Proceedings of the 22nd ACM International Conference on Computing Frontiers: Workshops and Special Sessions, 2025

A Dynamic Allocation Scheme for Adaptive Shared-Memory Mapping on Kilo-Core RV Clusters for Attention-Based Model Deployment.
Proceedings of the 36th IEEE International Conference on Application-specific Systems, 2025

2024
A 1024 RV-Cores Shared-L1 Cluster with High Bandwidth Memory Link for Low-Latency 6G-SDR.
CoRR, 2024

3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

2023
Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-Core Processor.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023


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