Bruno Rouzeyre
According to our database1,
Bruno Rouzeyre
authored at least 119 papers
between 1989 and 2022.
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Bibliography
2022
A Lightweight, Plug-and-Play and Autonomous JTAG Authentication IP for Secure Device Testing.
Proceedings of the IEEE European Test Symposium, 2022
2021
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
Proceedings of the 26th IEEE European Test Symposium, 2021
2020
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Des. Test, 2019
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019
Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019
2018
Microelectron. Reliab., 2018
Protection Against Hardware Trojans With Logic Testing: Proposed Solutions and Challenges Ahead.
IEEE Des. Test, 2018
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018
The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model.
Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2018
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018
2017
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017
Proceedings of the 22nd IEEE European Test Symposium, 2017
2016
ACM J. Emerg. Technol. Comput. Syst., 2016
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Figure of Merits of 28nm Si Technologies for Implementing Laser Attack Resistant Security Dedicated Circuits.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 20th IEEE European Test Symposium, 2015
Proceedings of the European Conference on Circuit Theory and Design, 2015
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS.
Microelectron. Reliab., 2014
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Layout-aware laser fault injection simulation and modeling: From physical level to gate level.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014
2013
ACM Trans. Design Autom. Electr. Syst., 2013
Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection.
Microelectron. Reliab., 2013
Inf. Secur. J. A Glob. Perspect., 2013
Inf. Secur. J. A Glob. Perspect., 2013
A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic.
J. Electron. Test., 2013
A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the 8th International Design and Test Symposium, 2013
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
2012
Proceedings of the Fault Analysis in Cryptography, 2012
Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode.
Microelectron. Reliab., 2012
J. Cryptogr. Eng., 2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
A scan-based attack on Elliptic Curve Cryptosystems in presence of industrial Design-for-Testability structures.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012
2011
Proceedings of the 12th Latin American Test Workshop, 2011
Proceedings of the HOST 2011, 2011
Proceedings of the 16th European Test Symposium, 2011
A New Bulk Built-In Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Evaluation of concurrent error detection techniques on the Advanced Encryption Standard.
Proceedings of the 15th European Test Symposium, 2010
Evaluation of Resistance to Differential Power Analysis: Execution Time Optimizations for Designers.
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010
Ensuring high testability without degrading security: Embedded tutorial on "test and security".
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
Proceedings of the Cryptographic Hardware and Embedded Systems, 2010
2009
A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard.
J. Electron. Test., 2009
Proceedings of the 10th Latin American Test Workshop, 2009
2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the 13th European Test Symposium, 2008
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
2007
Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007
A Dependable Parallel Architecture for SBoxes.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
2006
Scan Pattern Watermarking.
Proceedings of the 7th Latin American Test Workshop, 2006
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Fitting ATE Channels with Scan Chains: a Comparison between a Test Data Compression Technique and Serial Loading of Scan Chains.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
Proceedings of the 10th European Test Symposium, 2005
Proceedings of the 2005 Design, 2005
2004
Comput. Artif. Intell., 2004
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
Proceedings of the 9th European Test Symposium, 2004
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004
Proceedings of the 2004 Design, 2004
2003
Matching in the presence of don't cares and redundant sequential elements for sequential equivalence checking.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003
Proceedings of the 8th European Test Workshop, 2003
2002
VLSI Design, 2002
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002
Proceedings of the 2002 Design, 2002
Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification.
Proceedings of the 2002 Design, 2002
2001
A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis.
J. Electron. Test., 2001
Functional Test Generation using Constraint Logic Programming.
Proceedings of the SOC Design Methodologies, 2001
Power-Constrained Test Scheduling for SoCs Under a "no session" Scheme.
Proceedings of the SOC Design Methodologies, 2001
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001
2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
1998
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
Proceedings of the 1998 Design, 1998
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998
1997
J. Electron. Test., 1997
Proceedings of the European Design and Test Conference, 1997
1995
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995
Proceedings of the 1995 European Design and Test Conference, 1995
1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
1991
Proceedings of the conference on European design automation, 1991
High level synthesis: a data path partitioning method dedicated to speed enhancement.
Proceedings of the conference on European design automation, 1991
1989