Bruno Rouzeyre

According to our database1, Bruno Rouzeyre authored at least 104 papers between 1989 and 2018.

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Bibliography

2018
Assessing body built-in current sensors for detection of multiple transient faults.
Microelectronics Reliability, 2018

Protection Against Hardware Trojans With Logic Testing: Proposed Solutions and Challenges Ahead.
IEEE Design & Test, 2018

Encryption of test data: which cipher is better?
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

A New Secure Stream Cipher for Scan Chain Encryption.
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

SI ECCS: SECure context saving for IoT devices.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

2017
Experimentations on scan chain encryption with PRESENT.
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

Hacking the Control Flow error detection mechanism.
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

Scan chain encryption for the test, diagnosis and debug of secure circuits.
Proceedings of the 22nd IEEE European Test Symposium, 2017

2016
Frontside Versus Backside Laser Injection: A Comparative Study.
JETC, 2016

Using outliers to detect stealthy hardware trojan triggering?
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016

Hardware Trust through Layout Filling: A Hardware Trojan Prevention Technique.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015
3D DFT Challenges and Solutions.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Figure of Merits of 28nm Si Technologies for Implementing Laser Attack Resistant Security Dedicated Circuits.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Session-less based thermal-aware 3D-SIC test scheduling.
Proceedings of the 20th IEEE European Test Symposium, 2015

Hardware Trojan prevention using layout-level design approach.
Proceedings of the European Conference on Circuit Theory and Design, 2015

On the limitations of logic testing for detecting Hardware Trojans Horses.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

New testing procedure for finding insertion sites of stealthy hardware trojans.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Thwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison.
IEEE Trans. VLSI Syst., 2014

Test Versus Security: Past and Present.
IEEE Trans. Emerging Topics Comput., 2014

Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS.
Microelectronics Reliability, 2014

Built-in self-test for manufacturing TSV defects before bonding.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014



2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Customized cell detector for laser-induced-fault detection.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Layout-aware laser fault injection simulation and modeling: From physical level to gate level.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Laser attacks on integrated circuits: From CMOS to FD-SOI.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

2013
A novel differential scan attack on advanced DFT structures.
ACM Trans. Design Autom. Electr. Syst., 2013

Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection.
Microelectronics Reliability, 2013

Multilevel Ionizing-Induced Transient Fault Simulator.
Information Security Journal: A Global Perspective, 2013

On the Effectiveness of Hardware Trojan Horse Detection via Side-Channel Analysis.
Information Security Journal: A Global Perspective, 2013

Secure JTAG Implementation Using Schnorr Protocol.
J. Electronic Testing, 2013

A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic.
J. Electronic Testing, 2013

A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

A 3D IC BIST for pre-bond test of TSVs using ring oscillators.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

A smart test controller for scan chains in secure circuits.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

A BIST method for TSVs pre-bond test.
Proceedings of the 8th International Design and Test Symposium, 2013

A bulk built-in sensor for detection of fault attacks.
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Laser-Induced Fault Simulation.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
On Countermeasures Against Fault Attacks on the Advanced Encryption Standard.
Proceedings of the Fault Analysis in Cryptography, 2012

Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode.
Microelectronics Reliability, 2012

Scan attacks on side-channel and fault attack resistant public-key implementations.
J. Cryptographic Engineering, 2012

Are advanced DfT structures sufficient for preventing scan-attacks?
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

On-chip test comparison for protecting confidential data in secure ICs.
Proceedings of the 17th IEEE European Test Symposium, 2012

A scan-based attack on Elliptic Curve Cryptosystems in presence of industrial Design-for-Testability structures.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

A New Scan Attack on RSA in Presence of Industrial Countermeasures.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012

2011
New security threats against chips containing scan chain structures.
Proceedings of the HOST 2011, 2011

Scan Attacks and Countermeasures in Presence of Scan Response Compactors.
Proceedings of the 16th European Test Symposium, 2011

A New Bulk Built-In Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Power consumption traces realignment to improve differential power analysis.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010
Self-Test Techniques for Crypto-Devices.
IEEE Trans. VLSI Syst., 2010

Evaluation of concurrent error detection techniques on the advanced encryption standard.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Evaluation of concurrent error detection techniques on the Advanced Encryption Standard.
Proceedings of the 15th European Test Symposium, 2010

Evaluation of Resistance to Differential Power Analysis: Execution Time Optimizations for Designers.
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

Ensuring high testability without degrading security: Embedded tutorial on "test and security".
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

When Failure Analysis Meets Side-Channel Attacks.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2010

2009
A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard.
J. Electronic Testing, 2009

2008
Improving the Test of NoC-Based SoCs with Help of Compression Schemes.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

A Reliable Architecture for the Advanced Encryption Standard.
Proceedings of the 13th European Test Symposium, 2008

An Integrated Validation Environment for Differential Power Analysis.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2007
Securing Scan Control in Crypto Chips.
J. Electronic Testing, 2007

Mutation Sampling Technique for the Generation of Structural Test Data
CoRR, 2007

Compression-based SoC Test Infrastructures.
Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007

Test data compression and TAM design.
Proceedings of the IFIP VLSI-SoC 2007, 2007

A Dependable Parallel Architecture for SBoxes.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

An On-Line Fault Detection Scheme for SBoxes in Secure Circuits.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

A Novel Parity Bit Scheme for SBox in AES Circuits.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006
Secure Scan Techniques: A Comparison.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Fitting ATE Channels with Scan Chains: a Comparison between a Test Data Compression Technique and Serial Loading of Scan Chains.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

A secure scan design methodology.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Test control for secure scan designs.
Proceedings of the 10th European Test Symposium, ETS 2005, Tallinn, 2005

Mutation Sampling Technique for the Generation of Structural Test Data.
Proceedings of the 2005 Design, 2005

2004
A Flip-Flop Matching Engine to Verify Sequential Optimizations.
Computers and Artificial Intelligence, 2004

Scan Design and Secure Chip.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

User-constrained test architecture design for modular SOC testing.
Proceedings of the 9th European Test Symposium, 2004

On Using Test Vector Differences for Reducing Test Pin Numbers.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

An Arithmetic Structure for Test Data Horizontal Compression.
Proceedings of the 2004 Design, 2004

2003
Matching in the presence of don't cares and redundant sequential elements for sequential equivalence checking.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

2002
Improving Datapath Testability by Modifying Controller Specification.
VLSI Design, 2002

A simple and effective compression scheme for test pins reduction.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

A Heuristic for Test Scheduling at System Level.
Proceedings of the 2002 Design, 2002

Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification.
Proceedings of the 2002 Design, 2002

2001
A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis.
J. Electronic Testing, 2001

Functional Test Generation using Constraint Logic Programming.
Proceedings of the SOC Design Methodologies, 2001

Power-Constrained Test Scheduling for SoCs Under a "no session" Scheme.
Proceedings of the SOC Design Methodologies, 2001

Taylor expansion diagrams: a new representation for RTL verification.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

2000
BISTing data paths at behavioral level.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

A controller resynthesis based method for improving datapath testability.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
BISTing Datapaths under Heterogeneous Test Schemes.
J. Electronic Testing, 1999

1998
Low Cost Partial Scan Design: A High Level Synthesis Approach.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique.
Proceedings of the 1998 Design, 1998

Alleviating DFT Cost Using Testability Driven HLS.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
Improving Testability of Non-Scan Designs during Behavioral Synthesis.
J. Electronic Testing, 1997

Analyzing testability from behavioral to RT level.
Proceedings of the European Design and Test Conference, 1997

1995
Is High-Level Test Synthesis Just Design for Test?
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

High-level synthesis for easy testability.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
Component Selection, Scheduling and Control Schemes for High Level Synthesis.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Automatic Synthesis of BISTed Data Paths From High Level Specification.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1991
Optimization of micro-controllers by partitioning.
Proceedings of the conference on European design automation, 1991

High level synthesis: a data path partitioning method dedicated to speed enhancement.
Proceedings of the conference on European design automation, 1991

1989
Operators allocation in the silicon compiler SCOOP.
Integration, 1989


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