Marvin Damschen

Orcid: 0000-0002-6236-5799

According to our database1, Marvin Damschen authored at least 14 papers between 2014 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

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Bibliography

2019
Worst-Case Execution Time Guarantees for Runtime-Reconfigurable Architectures.
PhD thesis, 2019

WCET Guarantees for Opportunistic Runtime Reconfiguration.
Proceedings of the International Conference on Computer-Aided Design, 2019

Analyses and architectures for mixed-critical systems: industry trends and research perspective.
Proceedings of the International Conference on Embedded Software Companion, 2019

2018
Preemption of the Partial Reconfiguration Process to Enable Real-Time Computing With FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2018

Co-Scheduling on Fused CPU-GPU Architectures With Shared Last Level Caches.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017
Timing Analysis of Tasks on Runtime Reconfigurable Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2017

CoRQ: Enabling Runtime Reconfiguration Under WCET Guarantees for Real-Time Systems.
IEEE Embed. Syst. Lett., 2017

Auto-SI: An adaptive reconfigurable processor with run-time loop detection and acceleration.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Shallow Water Waves on a Deep Technology Stack: Accelerating a Finite Volume Tsunami Model Using Reconfigurable Hardware in Invasive Computing.
Proceedings of the Euro-Par 2017: Parallel Processing Workshops, 2017

2016
Extending the WCET Problem to Optimize for Runtime-Reconfigurable Processors.
ACM Trans. Archit. Code Optim., 2016

Invasive computing for timing-predictable stream processing on MPSoCs.
it Inf. Technol., 2016

2015
Floating point acceleration for stream processing applications in dynamically reconfigurable processors.
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015

Transparent offloading of computational hotspots from binary code to Xeon Phi.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Easy-to-Use On-the-Fly Binary Program Acceleration on Many-Cores.
CoRR, 2014


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