Lars Bauer
Orcid: 0000-0003-0253-4594Affiliations:
- Karlsruhe Institute of Technology, Germany
According to our database1,
Lars Bauer
authored at least 103 papers
between 2007 and 2024.
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Bibliography
2024
CoRR, 2024
Covert-Hammer: Coordinating Power-Hammering on Multi-tenant FPGAs via Covert Channels.
Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024
2023
IEEE Embed. Syst. Lett., December, 2023
IEEE Embed. Syst. Lett., December, 2023
ACM Trans. Embed. Comput. Syst., October, 2023
Cache-Based Side-Channel Attack Mitigation for Many-Core Distributed Systems via Dynamic Task Migration.
IEEE Trans. Inf. Forensics Secur., 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
Proceedings of the International Conference on Microelectronics, 2023
The First Concept and Real-world Deployment of a GPU-based Thermal Covert Channel: Attack and Countermeasures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Late Breaking Results: Configurable Ring Oscillators as a Side-Channel Countermeasure.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Smart Detection of Obfuscated Thermal Covert Channel Attacks in Many-core Processors.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications.
Proceedings of the International Conference on Compilers, 2023
2022
ACM Trans. Embed. Comput. Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
ARMOR: A Reliable and Mobility-Aware RPL for Mobile Internet of Things Infrastructures.
IEEE Internet Things J., 2022
CoRR, 2022
2021
LoopBreaker: Disabling Interconnects to Mitigate Voltage-Based Attacks in Multi-Tenant FPGAs.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Improved Feature Extraction Method for Sound Recognition Applied to Automatic Sorting of Recycling Wastes.
J. Inf. Process., 2020
Hierarchical Classification for Constrained IoT Devices: A Case Study on Human Activity Recognition.
IEEE Internet Things J., 2020
CoRR, 2020
Impacts of Mobility Models on RPL-Based Mobile IoT Infrastructures: An Evaluative Comparison and Survey.
IEEE Access, 2020
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020
2019
ACM Trans. Internet Techn., 2019
IEEE Internet Things J., 2019
Proceedings of the International Conference on Computer-Aided Design, 2019
Analyses and architectures for mixed-critical systems: industry trends and research perspective.
Proceedings of the International Conference on Embedded Software Companion, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Preemption of the Partial Reconfiguration Process to Enable Real-Time Computing With FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2018
ACM Trans. Cyber Phys. Syst., 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Efficient Partial Online Synthesis of Special Instructions for Reconfigurable Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Computers, 2017
IEEE Embed. Syst. Lett., 2017
Auto-SI: An adaptive reconfigurable processor with run-time loop detection and acceleration.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
Shallow Water Waves on a Deep Technology Stack: Accelerating a Finite Volume Tsunami Model Using Reconfigurable Hardware in Invasive Computing.
Proceedings of the Euro-Par 2017: Parallel Processing Workshops, 2017
Ultra-low power and dependability for IoT devices (Invited paper for IoT technologies).
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
ACM Trans. Archit. Code Optim., 2016
it Inf. Technol., 2016
it Inf. Technol., 2016
Proceedings of the 3rd IEEE World Forum on Internet of Things, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016
2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
J. Syst. Archit., 2015
it Inf. Technol., 2015
STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Floating point acceleration for stream processing applications in dynamically reconfigurable processors.
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015
Online binding of applications to multiple clock domains in shared FPGA-based systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015
2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 2014 International Conference on Compilers, 2014
COREFAB: Concurrent reconfigurable fabric utilization in heterogeneous multi-core systems.
Proceedings of the 2014 International Conference on Compilers, 2014
2013
IEEE Trans. Computers, 2013
Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures.
Proceedings of the 2013 IEEE International Test Conference, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013
Proceedings of the International Conference on Compilers, 2013
Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies.
Proceedings of the International Conference on Compilers, 2013
2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
OTERA: Online test strategies for reliable reconfigurable architectures - Invited paper for the AHS-2012 special session "Dependability by reconfigurable hardware".
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012
2011
Run-Time Resource Allocation for Simultaneous Multi-tasking in Multi-core Reconfigurable Processors.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011
Minority-Game-based resource allocation for run-time reconfigurable multi-core processors.
Proceedings of the Design, Automation and Test in Europe, 2011
mRTS: Run-time system for reconfigurable processors with multi-grained instruction-set extensions.
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
Adaptive resource management for simultaneous multitasking in mixed-grained reconfigurable multi-core processors.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
Concepts, architectures, and run-time systems for efficient and adaptive reconfigurable processors.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011
Springer, ISBN: 978-1-4419-7411-2, 2011
2010
Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms.
J. Signal Process. Syst., 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
enBudget: A Run-Time Adaptive Predictive Energy-Budgeting scheme for energy-aware Motion Estimation in H.264/MPEG-4 AVC video encoder.
Proceedings of the Design, Automation and Test in Europe, 2010
KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture.
Proceedings of the Design, Automation and Test in Europe, 2010
2009
REMiS: Run-time energy minimization scheme in a reconfigurable processor with dynamic power-gated instruction set.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
A parallel approach for high performance hardware design of intra prediction in H.264/AVC Video Codec.
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009
2008
Efficient Resource Utilization for an Extensible Processor Through Dynamic Instruction Set Adaptation.
IEEE Trans. Very Large Scale Integr. Syst., 2008
3-tier dynamically adaptive power-aware motion estimator for h.264/AVC video encoding.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor.
Proceedings of the FPL 2008, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the 45th Design Automation Conference, 2008
2007
Proceedings of the First International Conference on Self-Adaptive and Self-Organizing Systems, 2007
An Optimized Application Architecture of the H.264 Video Encoder for Application Specific Platforms.
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007
Proceedings of the 44th Design Automation Conference, 2007