Michael Laisne

Affiliations:
  • Qualcomm, USA


According to our database1, Michael Laisne authored at least 11 papers between 2006 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2022
IEEE P1687.1: Extending the Network Boundaries for Test.
Proceedings of the IEEE International Test Conference, 2022

2020
Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices.
Proceedings of the IEEE International Test Conference, 2020

Modeling Novel Non-JTAG IEEE 1687-Like Architectures.
Proceedings of the IEEE International Test Conference, 2020

2017
Generalizing Access to Instrumentation Embedded in a Semiconductor Device.
Computer, 2017

Single-pin test control for Big A, little D devices.
Proceedings of the IEEE International Test Conference, 2017

2011
Advanced methods for leveraging new test standards.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Wafer probe test cost reduction of an RF/A device by automatic testset minimization - A case study.
Proceedings of the 2011 IEEE International Test Conference, 2011

2007
Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Verification and debugging of IDDQ test of low power chips.
Proceedings of the 2007 IEEE International Test Conference, 2007

Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2006
IEEE P1687: Toward Standardized Access of Embedded Instrumentation.
Proceedings of the 2006 IEEE International Test Conference, 2006


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