Alfred L. Crouch

Orcid: 0000-0001-5846-2417

According to our database1, Alfred L. Crouch authored at least 46 papers between 1989 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2022
IEEE P1687.1: Extending the Network Boundaries for Test.
Proceedings of the IEEE International Test Conference, 2022

2021
3D Ring Oscillator Based Test Structures to Detect a Trojan Die in a 3D Die Stack in the Presence of Process Variations.
IEEE Trans. Emerg. Top. Comput., 2021

2020
A role for embedded instrumentation in real-time hardware assurance and online monitoring against cybersecurity threats.
IEEE Instrum. Meas. Mag., 2020

Modeling Novel Non-JTAG IEEE 1687-Like Architectures.
Proceedings of the IEEE International Test Conference, 2020

2019
Innovative Practices on IEEE 1687.xyz.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Innovate Practices on CyberSecurity of Hardware Semiconductor Devices.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

2018
Innovative practices on machine learning for emerging applications.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

2017
Generalizing Access to Instrumentation Embedded in a Semiconductor Device.
Computer, 2017

Mitigating simple power analysis attacks on LSIB key logic.
Proceedings of the 2017 IEEE North Atlantic Test Workshop, 2017

Detecting a trojan die in 3D stacked integrated circuits.
Proceedings of the 2017 IEEE North Atlantic Test Workshop, 2017

Increasing IJTAG bandwidth and managing security through parallel locking-SIBs.
Proceedings of the IEEE International Test Conference, 2017

2016
Using Existing Reconfigurable Logic in 3D Die Stacks for Test.
Proceedings of the 25th IEEE North Atlantic Test Workshop, 2016

Invited - A box of dots: using scan-based path delay test for timing verification.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
A call to action: Securing IEEE 1687 and the need for an IEEE test Security Standard.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

2014
Board security enhancement using new locking SIB-based architectures.
Proceedings of the 2014 International Test Conference, 2014

Making it harder to unlock an LSIB: Honeytraps and misdirection in a P1687 network.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
FPGA-Based Embedded Tester with a P1687 Command, Control, and Observe-System.
IEEE Des. Test, 2013

Don't forget to lock your SIB: Hiding instruments using P16871.
Proceedings of the 2013 IEEE International Test Conference, 2013

BA-BIST: Board test from inside the IC out.
Proceedings of the 2013 IEEE International Test Conference, 2013

2012
Board assisted-BIST: Long and short term solutions for testpoint erosion - Reaching into the DFx toolbox.
Proceedings of the 2012 IEEE International Test Conference, 2012

2009
We need more standards like IEEE 1500.
IEEE Des. Test Comput., 2009

IEEE P1687 IJTAG a presentation of current technology.
Proceedings of the 2009 IEEE International Test Conference, 2009

2008
The Advantages of Limiting P1687 to a Restricted Subset.
Proceedings of the 2008 IEEE International Test Conference, 2008

2007
A Production IR-Drop Screen on a Chip.
IEEE Des. Test Comput., 2007

IJTAG: The path to organized instrument connectivity.
Proceedings of the 2007 IEEE International Test Conference, 2007

Separating temperature effects from ring-oscillator readings to measure true IR-drop on a chip.
Proceedings of the 2007 IEEE International Test Conference, 2007

Processing High Volume Scan Test Results for Yield Learning.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2006
IEEE P1687: Toward Standardized Access of Embedded Instrumentation.
Proceedings of the 2006 IEEE International Test Conference, 2006

Characterize Predicted vs Actual IR Drop in a Chip Using Scan Clocks.
Proceedings of the 2006 IEEE International Test Conference, 2006

2005
IJTAG (internal JTAG): a step toward a DFT standard.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004
Future Trends in Test: The Adoption and Use of Low Cost Structural Testers.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
AC Scan Path Selection for Physical Debugging.
IEEE Des. Test Comput., 2003

2002
Testing the Tester: What Broke? Where? When? Why?
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001
Very Low Cost Testers: Opportunities and Challenges.
IEEE Des. Test Comput., 2001

2000
Test Development for a Third-Version ColdFire Microprocessor.
IEEE Des. Test Comput., 2000

Optimization trade-offs for vector volume and test power.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999
The DFT Psychic Network.
IEEE Des. Test Comput., 1999

The testability features of the 3rd generation ColdFire family of microprocessors.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
Test Development for Second-Generation ColdFire Microprocessors.
IEEE Des. Test Comput., 1998

Best Methods for At-Speed Testing?
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

1997
Designing and Verifying Embedded Microprocessors.
IEEE Des. Test Comput., 1997

A Case Study of the Test Development for the 2nd Generation ColdFire® Microprocessors.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1995
The superscalar architecture of the MC68060.
IEEE Micro, 1995

1994
Low-Power Mode and IEEE 1149.1 Compliance - A Low-Power Solution.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Testabilty Features of the MC 68060 Microprocessor.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1989
Prototype Testing Simplified by Scannable Buffers and Latches.
Proceedings of the Proceedings International Test Conference 1989, 1989


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