Yufei Ma

According to our database, Yufei Ma authored at least 31 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing.

Ying Liu, Yufei Ma, Ninghui Shang, Tianhao Zhao, Peiyu Chen, Meng Wu, Jiayoon Ru, Tianyu Jia, Le Ye, Zhixuan Wang, Ru Huang

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

Research progress on low-power artificial intelligence of things (AIoT) chip design.

Le Ye, Zhixuan Wang, Tianyu Jia, Yufei Ma, Linxiao Shen, Yihan Zhang, Heyi Li, Peiyu Chen, Meng Wu, Ying Liu, Yiqi Jing, Hao Zhang, Ru Huang

Sci. China Inf. Sci., October, 2023

An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique.

Ying Liu, Yufei Ma, Wei He, Zhixuan Wang, Linxiao Shen, Jiayoon Ru, Ru Huang, Le Ye

IEEE Trans. Circuits Syst. I Regul. Pap., 2023

A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing.

Peiyu Chen, Meng Wu, Wentao Zhao, Jiajia Cui, Zhixuan Wang, Yadong Zhang, Qijun Wang, Jiayoon Ru, Linxiao Shen, Tianyu Jia, Yufei Ma, Le Ye, Ru Huang

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

DCIM-3DRec: A 3D Reconstruction Accelerator with Digital Computing-in-Memory and Octree-Based Scheduler.

Yiqi Jing, Yiyang Sun, Xiao Wang, Wentao Zhao, Meng Wu, Fengyun Yan, Yufei Ma, Le Ye, Tianyu Jia

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware.

Yanchi Dong, Tianyu Jia, Kaixuan Du, Yiqi Jing, Qijun Wang, Pixian Zhan, Yadong Zhang, Fengyun Yan, Yufei Ma, Yun Liang, Le Ye, Ru Huang

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

A A 22nm 0.43pJ/SOP Sparsity-Aware In-Memory Neuromorphic Computing System with Hybrid Spiking and Artificial Neural Network and Configurable Topology.

Ying Liu, Zhiyuan Chenl, Zhixuan Wang, Wentao Zhao, Wei He, Jianfeng Zhu, Oijun Wang, Ning Zhang, Tianyu Jia, Yufei Ma, Le Ye, Ru Huang

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

RIMAC: An Array-Level ADC/DAC-Free ReRAM-Based in-Memory DNN Processor with Analog Cache and Computation.

Peiyu Chen, Meng Wu, Yufei Ma, Le Ye, Ru Huang

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

A Flexible and Efficient FPGA Accelerator for Various Large-Scale and Lightweight CNNs.

Xiao Wu, Yufei Ma, Meiqi Wang, Zhongfeng Wang

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Hybrid Stochastic-Binary Computing for Low-Latency and High-Precision Inference of CNNs.

Zhiyuan Chen, Yufei Ma, Zhongfeng Wang

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

DCIM-GCN: Digital Computing-in-Memory to Efficiently Accelerate Graph Convolutional Networks.

Yikan Qiu, Yufei Ma, Wentao Zhao, Meng Wu, Le Ye, Ru Huang

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2021

SWIFT: Small-World-based Structural Pruning to Accelerate DNN Inference on FPGA.

Yufei Ma, Gokul Krishnan, Yu Cao, Le Ye, Ru Huang

Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

2020

Performance Modeling for CNN Inference Accelerators on FPGA.

Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-Sun Seo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators.

Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-Sun Seo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Efficient Inference of Large-Scale and Lightweight Convolutional Neural Networks on FPGA.

Xiao Wu, Yufei Ma, Zhongfeng Wang

Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

Efficient Hardware Post Processing of Anchor-Based Object Detection on FPGA.

Hui Zhang, Wei Wu, Yufei Ma, Zhongfeng Wang

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Optimizing Stochastic Computing for Low Latency Inference of Convolutional Neural Networks.

Zhiyuan Chen, Yufei Ma, Zhongfeng Wang

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

In-Memory Computing: The Next-Generation AI Computing Paradigm.

Yufei Ma, Yuan Du, Li Du, Jun Lin, Zhongfeng Wang

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

An Efficient FPGA Accelerator Optimized for High Throughput Sparse CNN Inference.

Jiayu Wen, Yufei Ma, Zhongfeng Wang

Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

2019

Efficient Network Construction Through Structural Plasticity.

Xiaocong Du, Zheng Li, Yufei Ma, Yu Cao

IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Automatic Compiler Based FPGA Accelerator for CNN Training.

Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2018

Hardware Acceleration of Deep Convolutional Neural Networks on FPGA.

Yufei Ma

PhD thesis, 2018

Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA.

Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo

IEEE Trans. Very Large Scale Integr. Syst., 2018

ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler.

Yufei Ma, Naveen Suda, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo

Integr., 2018

Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs.

Yufei Ma, Tu Zheng, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo

Proceedings of the International Conference on Computer-Aided Design, 2018

2017

End-to-end scalable FPGA accelerator for deep residual networks.

Yufei Ma, Minkyu Kim, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks.

Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks.

Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2016

Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA.

Yufei Ma, Naveen Suda, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks.

Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015

Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits.

Yufei Ma, Minkyu Kim, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015