Nihar Dasari

According to our database1, Nihar Dasari authored at least 5 papers between 2019 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse.
IEEE Trans. Very Large Scale Integr. Syst., 2020

2019
Automatic GDSII Generator for On-Chip Voltage Regulator for Easy Integration in Digital SoCs.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

On the Effect of NBTI Induced Aging of Power Stage on the Transient Performance of On-Chip Voltage Regulators.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

A Spectral Convolutional Net for Co-Optimization of Integrated Voltage Regulators and Embedded Inductors.
Proceedings of the International Conference on Computer-Aided Design, 2019

Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019


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