Venakata Chaitanya Krishna Chekuri
Orcid: 0000-0002-3175-3350
According to our database1,
Venakata Chaitanya Krishna Chekuri
authored at least 16 papers
between 2018 and 2022.
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Bibliography
2022
IEEE Trans. Ind. Electron., 2022
Analysis of the Effect of Hot Carrier Injection in An Integrated Inductive Voltage Regulator.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022
2020
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse.
IEEE Trans. Very Large Scale Integr. Syst., 2020
An Inductive Voltage Regulator With Overdrive Tracking Across Input Voltage in Cascoded Power Stage.
IEEE Trans. Circuits Syst., 2020
Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO.
IEEE J. Solid State Circuits, 2020
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
Silicon vs. Organic Interposer: PPA and Reliability Tradeoffs in Heterogeneous 2.5D Chiplet Integration.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
A Configurable Dual-Mode PRINCE Cipher with Security Aware Pipelining in 65nm for High Throughput Applications.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
A Fully Synthesized Integrated Buck Regulator with Auto-generated GDS-II in 65nm CMOS Process.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
Autotuning of Integrated Inductive Voltage Regulator Using On-Chip Delay Sensor to Tolerate Process and Passive Variations.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Automatic GDSII Generator for On-Chip Voltage Regulator for Easy Integration in Digital SoCs.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
On the Effect of NBTI Induced Aging of Power Stage on the Transient Performance of On-Chip Voltage Regulators.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
A Spectral Convolutional Net for Co-Optimization of Integrated Voltage Regulators and Embedded Inductors.
Proceedings of the International Conference on Computer-Aided Design, 2019
Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Performance based tuning of an inductive integrated voltage regulator driving a digital core against process and passive variations.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018