Peng Li

Orcid: 0000-0002-5983-2384

Affiliations:

Tsinghua University, Suzhou Automotive Research Institute, Vehicle Technology Group, Beijing, China
University of California at Los Angeles, Department of Computer Science, CA, USA (former)
Peking University, Computer Science Department, Center for Energy-Efficient Computing and Applications, Beijing, China (former)
Tsinghua University, Beijing, China (PhD 2008)

According to our database¹, Peng Li authored at least 32 papers between 2006 and 2022.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2022

A Closed-Loop Perception, Decision-Making and Reasoning Mechanism for Human-Like Navigation.

[BibT_eX]

[DOI]

Proceedings of the Thirty-First International Joint Conference on Artificial Intelligence, 2022

2021

Learning to Navigate in a VUCA Environment: Hierarchical Multi-expert Approach.

[BibT_eX]

[DOI]

CoRR, 2021

Sanger: A Co-Design Framework for Enabling Sparse Attention using Reconfigurable Architecture.

[BibT_eX]

[DOI]

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Learning to Navigate in a VUCA Environment: Hierarchical Multi-expert Approach.

[BibT_eX]

[DOI]

Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2021

Deep Reinforcement Learning for Multi-contact Motion Planning of Hexapod Robots.

[BibT_eX]

[DOI]

Proceedings of the Thirtieth International Joint Conference on Artificial Intelligence, 2021

2020

Making Robots Draw A Vivid Portrait In Two Minutes.

[BibT_eX]

[DOI]

Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2020

2017

HLScope+, : Fast and accurate performance estimation for FPGA HLS.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016

An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Statistical Cache Bypassing for Non-Volatile Memory.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

2015

FPGA Acceleration for Simultaneous Image Reconstruction and Segmentation based on the Mumford-Shah Regularization (Abstract Only).

[BibT_eX]

[DOI]

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Resource-Aware Throughput Optimization for High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

2014

SBAC: a statistics based cache bypassing method for asymmetric-access caches.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Theory and algorithm for generalized memory partitioning in high-level synthesis.

[BibT_eX]

[DOI]

Yuxin Wang

Peng Li

Jason Cong

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Transformations for throughput optimization in high-level synthesis (abstract only).

[BibT_eX]

[DOI]

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

FPGA Acceleration for Simultaneous Medical Image Reconstruction and Segmentation.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

An Optimal Microarchitecture for Stencil Computation Acceleration Based on Non-Uniform Partitioning of Data Reuse Buffers.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

A Hierarchical Architectural Framework for Reconfigurable Logic Computing.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Improving high level synthesis optimization opportunity through polyhedral transformations.

[BibT_eX]

[DOI]

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Automatic multidimensional memory partitioning for FPGA-based accelerators (abstract only).

[BibT_eX]

[DOI]

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Memory partitioning for multidimensional arrays in high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Improving polyhedral code generation for high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

2012

Memory partitioning and scheduling co-optimization in behavioral synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2010

Performance characterization and acceleration of Optical Character Recognition on handheld platforms.

[BibT_eX]

[DOI]

Proceedings of the 2010 IEEE International Symposium on Workload Characterization, 2010

Pattern-Unit Based Regular Expression Matching with Reconfigurable Function Unit.

[BibT_eX]

[DOI]

Proceedings of the Computational Science and Its Applications, 2010

2009

HMMer acceleration using systolic array based reconfigurable architecture.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2007

Exploit Temporal Locality of Shared Data in SRC Enabled CMP.

[BibT_eX]

[DOI]

Proceedings of the Network and Parallel Computing, IFIP International Conference, 2007

LIRAC: Using Live Range Information to Optimize Memory Access.

[BibT_eX]

[DOI]

Proceedings of the Architecture of Computing Systems, 2007

2006

Seamless Peripherals Integration for Network Computers based on the Reversed Server Message Block Protocol.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Networking and Services (ICNS 2006), 2006

SRC-based Cache Coherence Protocol in Chip Multiprocessor.

[BibT_eX]

[DOI]

Haixia Wang

Dongsheng Wang

Peng Li

Proceedings of the Japan-China Joint Workshop on Frontier of Computer Science and Technology, 2006

Acceleration Techniques for Chip-Multiprocessor Simulator Debug.

[BibT_eX]

[DOI]

Haixia Wang

Dongsheng Wang

Peng Li

Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

Live Range Aware Cache Architecture.

[BibT_eX]

[DOI]

Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

Peng Li

Timeline

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