Peter Hazucha

According to our database, Peter Hazucha authored at least 16 papers between 2000 and 2009.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2009

A Delay-Locked Loop Synchronization Scheme for High-Frequency Multiphase Hysteretic DC-DC Converters.

Pengfei Li, Lin Xue, Peter Hazucha, Tanay Karnik, Rizwan Bashirullah

IEEE J. Solid State Circuits, 2009

2008

A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction.

Jianping Xu, Peter Hazucha, Zuoguo Wu, Paolo A. Aseron, Mingwei Huang, Fabrice Paillet, Gerhard Schrom, James W. Tschanz, Vivek De, Tanay Karnik, Greg Taylor

IEEE J. Solid State Circuits, 2008

2007

High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters.

Peter Hazucha, Sung Tae Moon, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner, Saravanan Rajapandian, Tanay Karnik

IEEE J. Solid State Circuits, 2007

On-Die Supply-Resonance Suppression Using Band-Limited Active Damping.

Jianping Xu, Peter Hazucha, Mingwei Huang, Paolo A. Aseron, Fabrice Paillet, Gerhard Schrom, James W. Tschanz, Cangsang Zhao, Vivek De, Tanay Karnik, Greg Taylor

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Low Voltage Buffered Bandgap Reference.

Peter Hazucha, Fabrice Paillet, Sung Tae Moon, David J. Rennie, Gerhard Schrom, Donald S. Gardner, Kenneth Ikeda, Gell Gellman, Tanay Karnik

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2006

High-voltage power delivery through charge recycling.

Saravanan Rajapandian, Kenneth L. Shepard, Peter Hazucha, Tanay Karnik

IEEE J. Solid State Circuits, 2006

A Linear Regulator with Fast Digital Control for Biasing Integrated DC-DC Converters.

Peter Hazucha, Sung Tae Moon, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner, Saravanan Rajapandian, Tanay Karnik

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

High-frequency DC-DC conversion : fact or fiction.

Tanay Karnik, Peter Hazucha, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package.

Peter Hazucha, Gerhard Schrom, Jaehong Hahn, Bradley A. Bloechel, Paul Hack, Gregory E. Dermer, Siva G. Narendra, Donald S. Gardner, Tanay Karnik, Vivek De, Shekhar Borkar

IEEE J. Solid State Circuits, 2005

Area-efficient linear regulator with ultra-fast load regulation.

Peter Hazucha, Tanay Karnik, Bradley A. Bloechel, Colleen Parsons, David Finan, Shekhar Borkar

IEEE J. Solid State Circuits, 2005

2004

Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes.

Tanay Karnik, Peter Hazucha, Jagdish Patel

IEEE Trans. Dependable Secur. Comput., 2004

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V_T CMOS process.

Peter Hazucha, Tanay Karnik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Gregory E. Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar

IEEE J. Solid State Circuits, 2004

Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation.

Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald S. Gardner, Siva G. Narendra, Tanay Karnik, Vivek De

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

2003

Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process.

Peter Hazucha, Tanay Kamik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Greg Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2000

Cosmic-ray soft error rate characterization of a standard 0.6-μm CMOS process.

Peter Hazucha, Christer Svensson, Stephen A. Wender

IEEE J. Solid State Circuits, 2000

Optimized test circuits for SER characterization of a manufacturing process.

Peter Hazucha, Christer Svensson

IEEE J. Solid State Circuits, 2000