Greg Taylor

According to our database1, Greg Taylor authored at least 18 papers between 2004 and 2021.

Collaborative distances:



In proceedings 
PhD thesis 




Modelling and understanding count processes through a Markov-modulated non-homogeneous Poisson process framework.
Eur. J. Oper. Res., 2021

A 1-2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation.
IEEE J. Solid State Circuits, 2019

High Capacity On-Package Physical Link Considerations.
Proceedings of the 2019 IEEE Symposium on High-Performance Interconnects, 2019

Information-Seeking Strategies in Medicine Queries: A Clinical Eye-Tracking Study with Gaze-Cued Retrospective Think-Aloud Protocol.
Int. J. Hum. Comput. Interact., 2018

When the Winning Move is Not to Play: Games of Deterrence in Cyber Security.
Proceedings of the Decision and Game Theory for Security - 6th International Conference, 2015

Re: Search.
New Media Soc., 2013

How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A novel digital loop filter architecture for bang-bang ADPLL.
Proceedings of the IEEE 25th International SOC Conference, 2012

Modeling the response of Bang-Bang digital PLLs to phase error perturbations.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

HVM performance validation and DFM techniques used in a 32nm CMOS thermal sensor system.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Interpolated VCO design for a low bandwidth, low-jitter, self-biased PLL in 45 nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

A 1.05 V 1.6 mW, 0.45°C 3σ Resolution ΣΔ Based Temperature Sensor With Parasitic Resistance Compensation in 32 nm Digital CMOS Process.
IEEE J. Solid State Circuits, 2009

A 1.05V 1.6mW 0.45°C 3σ-resolution ΔΣ-based temperature sensor with parasitic-resistance compensation in 32nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction.
IEEE J. Solid State Circuits, 2008

On-Die Supply-Resonance Suppression Using Band-Limited Active Damping.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Advanced thermal sensing circuit and test techniques used in a high performance 65nm processor.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Temperature Sensor Design in a High Volume Manufacturing 65nm CMOS Digital Process.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

I/O Self-Leakage Test.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004