Pulkit Jain
According to our database1,
Pulkit Jain
authored at least 18 papers
between 2008 and 2022.
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Bibliography
2022
Design and Implementation of a Quantitative Network Health Monitoring and Recovery System.
Wirel. Pers. Commun., 2022
Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Bitline Precharge DACs and Compact Schmitt Trigger ADCs.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
Development of a Model for Review Sharing in the Context of Mobile Phone Purchase Amongst Indian Millennials.
Int. J. Asian Bus. Inf. Manag., 2021
GNC Analysis and Robotic Systems Configuration of Collision-free Earth Observation Satellites (CfEOS) Constellations.
CoRR, 2021
16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2019
A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 3.6Mb 10.1Mb/mm<sup>2</sup> Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2015
The Dependence of BTI and HCI-Induced Frequency Degradation on Interconnect Length and Its Circuit Level Implications.
IEEE Trans. Very Large Scale Integr. Syst., 2015
2014
IEEE Micro, 2014
2012
A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches.
IEEE J. Solid State Circuits, 2012
A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor.
IEEE J. Solid State Circuits, 2012
An array-based Chip Lifetime Predictor macro for gate dielectric failures in core and IO FETs.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
2011
A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches.
IEEE J. Solid State Circuits, 2011
A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
2008
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008