Marco A. Ramírez

Orcid: 0000-0002-9376-2893

Affiliations:
  • National Polytechnic Institute of Mexico, Mexico
  • Universitat Politècnica de Catalunya, Barcelona, Spain (PhD 2007)


According to our database1, Marco A. Ramírez authored at least 36 papers between 1996 and 2026.

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Timeline

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Bibliography

2026
UPSORT: Design and Analysis of Processing-in-Memory Sorting Algorithms using UPMEM.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2026

2024
Proactive Load Balancing to Reduce Unnecessary Thread Migrations on Chip Multi-Processor (CMP) Systems.
Computación y Sistemas (CyS), 2024

2023
A Tool for Control Research Using Evolutionary Algorithm That Generates Controllers with a Pre-Specified Morphology.
Algorithms, July, 2023


2022
Measuring the Storing Capacity of Hyperdimensional Binary Vectors.
Computación y Sistemas, 2022

Lagarto I-Una plataforma hardware/software de arquitectura de computadoras para la academia e investigación.
CoRR, 2022

Adaptable Register File Organization for Vector Processors.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022


2021
Generating negations of probability distributions.
Soft Comput., 2021

Design and Installation of an IoT Electricity and Water Technological and Monitoring Solution.
Proceedings of the Smart Cities - 4th Ibero-American Congress, 2021

2020
A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures.
ACM Trans. Archit. Code Optim., 2020

Learning rules for Sugeno ANFIS with parametric conjunction operations.
Appl. Soft Comput., 2020

Semantic Similarity Estimation Using Vector Symbolic Architectures.
IEEE Access, 2020


2019
Exploring Storing Capacity of Hyperdimensional Binary Vectors.
Res. Comput. Sci., 2019

Lagarto I RISC-V Multi-core: Research Challenges to Build and Integrate a Network-on-Chip.
Proceedings of the Supercomputing, 2019

IPN Sustainability Program: Solar Photovoltaic Electricity Generation and Consumption Reduction.
Proceedings of the Smart Cities - Second Ibero-American Congress, 2019

2017
Lagarto I - Una plataforma hardware/software de arquitectura de computadoras para la academia e investigación.
Res. Comput. Sci., 2017

Sequence Prediction with Hyperdimensional Computing.
Res. Comput. Sci., 2017

An Automatic Functional Coverage for Digital Systems Through a Binary Particle Swarm Optimization Algorithm with a Reinitialization Mechanism.
J. Electron. Test., 2017

2015
Hardware Design of Digital Parametric Conjunctors and t-Norms.
Int. J. Fuzzy Syst., 2015

Automated Functional Test Generation for Digital Systems Through a Compact Binary Differential Evolution Algorithm.
J. Electron. Test., 2015

2013
Clustering Time Series by Wavelet and Evolutionary Computing.
Res. Comput. Sci., 2013

2012
A Hardware/Software Co-Execution Model Using Hardware Libraries for a SoPC Running Linux.
Res. Comput. Sci., 2012

A Reorder Buffer Design for High Performance Processors.
Computación y Sistemas, 2012

2011
FPGA Implementation of Fuzzy Mamdani System with Parametric Conjunctions Generated by Monotone Sum of Basic t-Norms.
Polibits, 2011

2008
A distributed processor state management architecture for large-window processors.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

2007
Fast and Accurate Signature-Generator for Detecting P2P Traffic.
Res. Comput. Sci., 2007

2005
A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2004
Instructions-Wake-Up mechanism: Power and Timing Evaluation.
Res. Comput. Sci., 2004

A partitioned instruction queue to reduce instruction wakeup energy.
Int. J. High Perform. Comput. Netw., 2004

2003
A Simple Low-Energy Instruction Wakeup Mechanism.
Proceedings of the High Performance Computing, 5th International Symposium, 2003

2001
Implementación de un Sistema de Control con Microcontrolador Difuso.
Polibits, 2001

1999
Diseño Moderno de Circuitos Digitales Usando DSP'S.
Polibits, 1999

1998
Despliegue de Imágenes en Paralelo a Través de Dos Monitores, Utilizando Dos Tarjetas de Video Modificadas.
Polibits, 1998

1996
Diseño y Construcción de un Controlador Lógico Programable Modular Orientado a Bus, en Base al 80188.
Polibits, 1996


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