Robert Balas

According to our database, Robert Balas authored at least 16 papers between 2020 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems.

Thomas Benz, Alessandro Ottaviano, Chaoqun Liang, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Davide Rossi, Luca Benini

IEEE Trans. Computers, September, 2025

A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications.

Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus A. Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gürkaynak, Davide Rossi, Luca Benini

CoRR, February, 2025

CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor.

Christopher Reinwardt, Robert Balas, Alessandro Ottaviano, Angelo Garofalo, Luca Benini

Proceedings of the 22nd ACM International Conference on Computing Frontiers, 2025

2024

CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers.

Robert Balas, Alessandro Ottaviano, Luca Benini

IEEE Trans. Very Large Scale Integr. Syst., June, 2024

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation.

Alessandro Ottaviano, Robert Balas, Giovanni Bambini, Antonio del Vecchio, Maicol Ciani, Davide Rossi, Luca Benini, Andrea Bartolini

Int. J. Parallel Program., April, 2024

ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package.

Alessandro Ottaviano, Robert Balas, Tim Fischer, Thomas Benz, Andrea Bartolini, Luca Benini

CoRR, 2024

SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications.

Michael Rogenmoser, Alessandro Ottaviano, Thomas Benz, Robert Balas, Matteo Perotti, Angelo Garofalo, Luca Benini

CoRR, 2024

vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-Criticality Systems.

Enrico Zelioli, Alessandro Ottaviano, Robert Balas, Nils Wistoff, Angelo Garofalo, Luca Benini

Proceedings of the 42nd IEEE International Conference on Computer Design, 2024

PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors.

Alessandro Ottaviano, Robert Balas, Philippe Sauter, Manuel Eggimann, Luca Benini

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs.

Thomas Benz, Alessandro Ottaviano, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Luca Benini

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

Towards a RISC-V Open Platform for Next-generation Automotive ECUs.

Luca Cuomo, Claudio Scordino, Alessandro Ottaviano, Nils Wistoff, Robert Balas, Luca Benini, Errico Guidieri, Ida Maria Savino

Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023

Well-being in Isolation: Exploring Artistic Immersive Virtual Environments in a Simulated Lunar Habitat to Alleviate Asthenia Symptoms.

Grzegorz Pochwatko, Wieslaw Kopec, Justyna Swidrak, Anna Jaskulska, Kinga H. Skorupska, Barbara Karpowicz, Rafal Maslyk, Maciej Grzeszczuk, Steven Barnes, Paulina Borkiewicz, Pawel Kobylinski, Michal Pabis-Orzeszyna, Robert Balas, Jagoda Lazarek, Florian Dufresne, Leonie Bensch, Tommy Nilsson

Proceedings of the IEEE International Symposium on Mixed and Augmented Reality, 2023

2022

ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration.

Alessandro Ottaviano, Robert Balas, Giovanni Bambini, Corrado Bonfanti, Simone Benatti, Davide Rossi, Luca Benini, Andrea Bartolini

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022

2021

Learning Affective Responses Through Evaluative Conditioning - New Developments in Affective Computing.

Robert Balas, Grzegorz Pochwatko

Proceedings of the Digital Interaction and Machine Intelligence - Proceedings of MIDI'2021, 2021

RISC-V for Real-time MCUs - Software Optimization and Microarchitectural Gap Analysis.

Robert Balas, Luca Benini

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

An Open-Source Scalable Thermal and Power Controller for HPC Processors.

Giovanni Bambini, Robert Balas, Christian Conficoni, Andrea Tilli, Luca Benini, Simone Benatti, Andrea Bartolini

Proceedings of the 38th IEEE International Conference on Computer Design, 2020