Rui Liu

Affiliations:
  • University of Saskatchewan, Department of Electrical and Computer Engineering, Saskatoon, Canada


According to our database1, Rui Liu authored at least 12 papers between 2014 and 2021.

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Bibliography

2021
Single Event Upset Evaluation for a 28-nm FDSOI SRAM Type Buffer in an ARM Processor.
J. Electron. Test., 2021

2018
Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree.
Microelectron. Reliab., 2018

2017
BPPT - Bulk potential protection technique for hardened sequentials.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

2016
A Built-in Single Event Upsets Detector for Sequential Cells.
J. Electron. Test., 2016

A 10-Transistor 65 nm SRAM Cell Tolerant to Single-Event Upsets.
J. Electron. Test., 2016

An SEU-Resilient SRAM Bitcell in 65-nm CMOS Technology.
J. Electron. Test., 2016

Total ionizing dose test facilities for micro-electronic circuits.
Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016

2015
A Novel Built-in Current Sensor for N-WELL SET Detection.
J. Electron. Test., 2015

Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology.
J. Electron. Test., 2015

Analysis of advanced circuits for SET measurement.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014
Single Event Resilient Dynamic Logic Designs.
J. Electron. Test., 2014

New approaches for synthesis of redundant combinatorial logic for selective fault tolerance.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014


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