Rita Fung

Affiliations:
  • Cisco Systems, San Jose, CA, USA


According to our database1, Rita Fung authored at least 10 papers between 2013 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Soft Error Characterization of D-FFs at the 5-nm Bulk FinFET Technology for the Terrestrial Environment.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

2021
Frequency, LET, and Supply Voltage Dependence of Logic Soft Errors at the 7-nm Node.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

Effects of Temperature and Supply Voltage on Soft Errors for 7-nm Bulk FinFET Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

2020
High-Current State triggered by Operating-Frequency Change.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Thermal Neutron Induced Soft Errors in 7-nm Bulk FinFET Node.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Using Partial Duplication With Compare to Detect Radiation-Induced Failure in a Commercial FPGA-Based Networking System.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Temperature Dependence of Single-Event Transient Pulse Widths for 7-nm Bulk FinFET Technology.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2015
Analysis of advanced circuits for SET measurement.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014
Single Event Resilient Dynamic Logic Designs.
J. Electron. Test., 2014

2013
Networking industry trends in ESD protection for high speed IOs.
Proceedings of the IEEE 10th International Conference on ASIC, 2013


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